The final publication is available at Springer via http://dx.doi.org/10.1007/978-3-642-54420-0_45Unlike other previous techniques, the recently proposed Hard Error Recovery (HER) fault-tolerant cache provides 100% fault-coverage in L1 data caches. This full coverage makes the HER cache appropiate for fault-dominated future technology nodes. An n-way set-associative HER cache implements one cache way with fast SRAM banks and the remaining ways with eDRAM banks to address power and area. Since the number of eDRAM cache blocks used in a specific HER cache organization depends on the cache associativity (i.e., the implemented number of ways), we expect that the performance and energy consumption provided by a given HER cache design st...
© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for a...
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
[[abstract]]Conventional set‐associative caches, with higher associativity, provide lower miss rates...
[EN] The cache hierarchy of current multicores typically consists of three levels, ranging from the ...
The final publication is available at Springer via http://dx.doi.org/10.1007/s11227-014-1288-5Power...
textModern microprocessors devote a large portion of their chip area to caches in order to bridge t...
This thesis presents novel methods based on a combination of well-known statistical techniques for f...
Memory systems are signicant contributors to the overall power requirements, energy consumption, and...
©2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for al...
The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity be...
textOne of the major limiters to computer systems and systems on chip (SOC) designs is accessing the...
The final publication is available at Springer via http://dx.doi.org/10.1007/s11227-014-1332-5As th...
Computers have changed our lives beyond our own imagination in the past several decades. The continu...
As the transistor budgets outpace the power envelope (the power-wall issue), new architectural and m...
Cache memories play a critical role in bridging the latency, bandwidth, and energy gaps between core...
© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for a...
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
[[abstract]]Conventional set‐associative caches, with higher associativity, provide lower miss rates...
[EN] The cache hierarchy of current multicores typically consists of three levels, ranging from the ...
The final publication is available at Springer via http://dx.doi.org/10.1007/s11227-014-1288-5Power...
textModern microprocessors devote a large portion of their chip area to caches in order to bridge t...
This thesis presents novel methods based on a combination of well-known statistical techniques for f...
Memory systems are signicant contributors to the overall power requirements, energy consumption, and...
©2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for al...
The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity be...
textOne of the major limiters to computer systems and systems on chip (SOC) designs is accessing the...
The final publication is available at Springer via http://dx.doi.org/10.1007/s11227-014-1332-5As th...
Computers have changed our lives beyond our own imagination in the past several decades. The continu...
As the transistor budgets outpace the power envelope (the power-wall issue), new architectural and m...
Cache memories play a critical role in bridging the latency, bandwidth, and energy gaps between core...
© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for a...
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
[[abstract]]Conventional set‐associative caches, with higher associativity, provide lower miss rates...