Non-binary LDPC decoder based on simplified enhanced generalized bit flipping algorithm

A simplified version of the enhanced serial generalized bit-flipping algorithm is proposed in this brief. This new algorithm reduces the quantity of information that is stored with a negligible performance loss of 0.05 dB compared with previous proposals. In addition, the algorithm allows us not only to save memory, but also to reduce the number of arithmetic resources needed. In addition, a new initialization of the algorithm avoids using techniques to control data growth without any performance degradation, reduces routing, increasing the maximum frequency achievable, and saves logic. The decoder derived from the simplified algorithm requires almost half the area of previous architectures, with a throughput of 716 Mbps on a 90-nm CMOS process for the (837, 723) nonbinary code over GF(32) at ten iterations.Manuscript received December 26, 2012; revised May 21, 2013; accepted July 25, 2013. Date of publication August 21, 2013; date of current version May 20, 2014. This work was supported in part by the Spanish Ministerio de Ciencia e Innovacion under Grant TEC2011-27916 and in part by the Universidad Politecnica de Valencia under Grant PAID-06-2012-SP20120625. The work of F. Garcia-Herrero was supported by the Spanish Ministerio de Educacion under Grant AP2010-5178.García Herrero, FM.; Canet Subiela, MJ.; Valls Coquillat, J. (2014). Non-binary LDPC decoder based on simplified enhanced generalized bit flipping algorithm. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22(6):1455-1459. https://doi.org/10.1109/TVLSI.2013.22760671455145922