Architecture of Generalized Bit-Flipping Decodingfor High-Rate Non-binary LDPC Codes

A VLSI architecture for the generalized bit-flipping decoding algorithm for non-binary low-density parity-check codes is proposed in this paper. The tentative decoding steps of the algorithm have been modifed to avoid computing and storing a matrix of dimension N ×2q , for a code (N,K) over GF(2q ), reducing its complexity with a minimal penalization of its performance, less than 0.05 dB compared with the original algorithm. The architecture was synthesized using a 90 nm standard cell library, for the (837, 723) non-binary code over GF(25), requiring 590220 xor gates and achieving a throughput of 89Mbps. Additionally, it was implemented in a Virtex- VI FPGA device with a cost of 4070 slices and a throughput of 44.6 Mbps.This research was supported by FEDER and the Spanish Ministerio de Ciencia e Innovacion, under Grant No. TEC2008-06787 and TEC2011-27916. F. Garcia-Herrero has developed his work in this project thanks to a VALi+d grant sponsored by Generalitat Valenciana (Conselleria d'Educacio). Grant No. ACIF/2011/023 and a FPU grant sponsored by the Spanish Government Grant No. AP2010-5178.García Herrero, FM.; Canet Subiela, MJ.; Valls Coquillat, J. (2013). Architecture of Generalized Bit-Flipping Decodingfor High-Rate Non-binary LDPC Codes. Circuits, Systems, and Signal Processing. 32:727-741. https://doi.org/10.1007/s00034-012-9481-372774132C. Chen, B. Bai, X. Ma, X. Wang, A symbol-reliability based message-passing decoding algorithm for nonbinary LDPC codes over finite fields, in 6th International Symposium on Turbo Codes and Iterative Information Processing, 2010C. Chen, B. Bai, X. Wang, M. Xu, Nonbinary LDPC codes constructed based on a cyclic MDS code and a low-complexity nonbinary message-passing decoding algorithm. IEEE Commun. Lett. 14(3), 239–241 (2010)C. Chen, Q. Huang, C. Chao, S. Lin, Two low-complexity reliability-based message-passing algorithms for decoding non-binary LDPC codes. IEEE Trans. Commun. 58(11), 3140–3147 (2010)X. Chen, S. Lin, V. Akella, Efficient configurable decoder architecture for nonbinary Quasi-Cyclic LDPC codes. IEEE Trans. Circuits Syst. I, Regul. Pap. 59(1), 188–197 (2012)S. Lin, S. Song, Y. Tai, L. Lan, L. Zeng, Algebraic constructions of nonbinary quasi-cyclic LDPC codes. in International Conference on Communications, Circuits and Systems Proceedings, June 2006, pp. 1303–1308B. Liu, J. Gao, G. Dou, W. Tao, Weighted symbol-flipping decoding for nonbinary LDPC codes, in Second International Conference on Networks Security, Wireless Communications and Trusted Computing, 2010C. Spagnol, E. Popovici, W. Marnane, Hardware implementation of GF(2 m ) LDPC decoders. IEEE Trans. Circuits Syst. I 56(12), 2609–2620 (2009)A. Voicila, F. Verdier, D. Declercq, M. Fossorier, P. Urard, Architecture of a low-complexity non-binary LDPC decoder for high order fields, in Proc. Intl. Symp. on Commun. and Info. Technologies, Sydney, Australia, Oct. 2007X. Zhang, F. Cai, Reduced-complexity decoder architecture for nonbinary LDPC codes. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 19(7), 1229–1238 (2011)X. Zhang, F. Cai, S. Lin, Low-complexity reliability-based message-passing decoder architectures for non-binary LDPC codes. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 20(11), 1938–1950 (2012)X. Zhang, F. Cai, Reduced-complexity extended Min-sum check node processing for non-binary LDPC decoding, in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2010X. Zhang, F. Cai, Reduced-latency scheduling scheme for min-max non-binary LDPC decoding, in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Dec. 2010X. Zhang, F. Cai, Reduced-complexity check node processing for non-binary LDPC decoding, in IEEE Workshop on Signal Processing Systems (SIPS), Oct. 2010X. Zhang, F. Cai, Partial-parallel decoder architecture for quasi-cyclic non-binary LDPC codes, in IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP), March 2010X. Zhang, F. Cai, Efficient partial-parallel decoder architecture for quasi-cyclic nonbinary LDPC codes. IEEE Trans. Circuits Syst. I, Regul. Pap. 58(2), 402–414 (2011)X. Zhang, F. Cai, Low-complexity architectures for reliability-based message-passing non-binary LDPC decoding, in IEEE International Symposium on Circuits and Systems (ISCAS), May 2011D. Zhao, X. Ma, C. Chen, B. Bai, A low complexity decoding algorithm for majority-logic decodable nonbinary LDPC codes. IEEE Commun. Lett. 14(11), 1062–1064 (2011