Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes

This paper presents an architecture for high-throughput decoding of high-rate Low-Density Parity-Check (LDPC) codes. The proposed architecture is a modification of the sliced message passing (SMP) decoding architecture which overlaps the check-node and variable-node update stages, achieving a good tradeoff between area and throughput, and also, high hardware utilization efficiency (HUE). The proposed modification does not affect the performance of the SMP algorithm and yields an area reduction of 33%. As an example, SMP architecture and the proposed modification was synthesized in a 90 nm CMOS process for the 2048-bit LDPC code of the IEEE802.3an standard with 16 iterations achieving a throughput of 5.9 Gbps with 15.3 mm2 and 6.2 Gbps with 10.2 mm2, respectively.This research was supported by FEDER and Spanish Ministerio de Ciencia e Innovacion under Grant No. TEC2008-06787.Angarita Preciado, FE.; Sansaloni Balaguer, TM.; Canet Subiela, MJ.; Valls Coquillat, J. (2012). Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes. Journal of Signal Processing Systems. 66(2):99-104. https://doi.org/10.1007/s11265-011-0580-399104662Gallager, R. G. (1963). Low-density parity-check codes. MIT Press.Digital Video Broadcasting (DVB); second generation. ETSI EN 302 307, vol. 1.1, 2005.IEEE Draft Standard for Info. Tech.-Telecomm. and information exchange between systems-Local and MAN-Specific requirements-Part 11: Wireless LAN MAC and PHY Layer specifications. IEEE Standard. P802.11n, 2008.IEEE Standard for LAN and MAN Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems: PHY and MAC Layers for Combined Fixed and Mobile Operation in Licensed Bands. IEEE Standard. 802.16e, 2008.IEEE 10 GBase-T Task Force. http://grouper.ieee.org/groups/802/3/an/index.html .MacKay, D. J. C. (1999). Good error-correcting codes based on very sparse matrices. IEEE Transactions on Information Theory, 45, 399–431.Fossorier, M., Mihaljevic, M., & Imai, H. (1999). Reduced complexity iterative decoding of LDPC codes based on belief propagation. IEEE Transactions on Communications, 47–5, 673–680.Chen, J., Dholakia, A., Eleftheriou, E., Fossorier, M., & Hu, X.-Y. (2005). Reduced-complexity decoding of LDPC codes. IEEE Transactions on Communications, 53–8, 1288–1299.Wang, Z., & Cui, A. (2007). Low-complexity high-speed decoder design for quasi-cyclic ldpc codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15–1, 104–114.Howland, C., & Blanksby, A. (2001). Parallel decoding architectures for LDPC codes. Proc. IEEE ISCAS, 4, 742–745.Blanksby, A., & Howland, C. (2002). A 690-mw 1-gb/s 1024-b, rate-1/2 low-density parity-check code decoder. IEEE Journal of Solid-state Circuits, 37–3, 404–412.Darabiha, A., Carusoe, A. C., & Kschischang, F. R. (2005). Multi-gbit/sec LDPC decoders with reduced interconnect complexity. Proc. IEEE Int. Symp. on Curcuits Systems, 5, 5194–5197.Darabiha, A., Carusone, A., & Kschischang, F. R. (2008). Power reduction techniques for LDPC decoders. IEEE Journal of Solid-State Circuits, 43–8, 1835–1845.Mohsenin, T., Truong, D., & Baas, B. (2009) Multi-split-row threshold decoding implementations for LDPC codes. Proc. IEEE ISCAS, 2449–2452.Liu, L., & Shi, R. (2008). Sliced message passing: high throughput overlaped decoding of high-rate LDPC codes, IEEE Transactions on Circuits and Systems, 55, 3697–3710.Sha, J., Lin, J., Wang, Z., Li, L., & Gao, M. (2009). Decoder design for rs-based ldpc codes. IEEE Transactions on Circuits and Systems II, 56–9, 724–728.Mansour, M., & Shanbhag, N. (2003). High-throughput ldpc decoders. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11–6, 976–996.Zhang, J., & Fossorier, M. (2005). Shuffled iterative decoding. IEEE Transactions on Communications, 53–2, 209–213.Zhang, Z., Anantharam, V., Wainwright, M., & Nikolic, B. (2009). A 47 Gb/s LDPC decoder with improved low error rate performance. Proc. IEEE VLSI Circuits Symp. Kyoto. 286–287.Zhong, H., Xu, W., Xie, N., & Zhang, T. (2007). Area-efficient min-sum decoder design for high-rate quasi-cyclic LDPC codes in magnetic recording. IEEE Transactions on Magnetics, 43, 4117–4122.Tanner, R. M. (1981). A recursive approach to low complexity codes. IEEE Transactions on Information Theory, IT-27, 533–547.Djurdjevic, I., Xu, J., Abdel-Ghaffar, K., & Lin, S. (2003). A class of LDPC codes constructed based on Reed-Solomon codes with two information symbols. IEEE Communications Letters, 7, 317–319.Fossorier, M. P. C. (2004). Quasi-ciclyc LDPC codes from circular permutation matrices. IEEE Transactions on Information Theory, 50, 1788–1793