Modelling of the parametric yield in decananometer SRAM-Arrays

In today's decananometer (90 nm, 65 nm, ...), CMOS technologies variations of device parameters play an ever more important role. Due to the demand for low leakage systems, supply voltage is decreased on one hand and the transistor threshold voltage is increased on the other hand. This reduces the overdrive voltage of the transistors and leads to decreasing read and write security margins in static memories (SRAM). In addition, smaller dimensions of the devices lead to increasing variations of the device parameters, thus mismatch effects increase. It can be shown that local variations of the transistor parameters limit the functionality of circuits stronger than variations on a global scale or hard defects. We show a method to predict the yield for a large number of SRAM devices without time consuming Monte Carlo simulations in dependence of various parameters (Vdd, temperature, technology options, transistor dimensions, ...). This helps the designer to predict the yield for various system options and transistor dimensions, to choose the optimal solution for a specific product