This paper presents a reconfigurable receiver with frequency-independent blocker suppression in a 40nm CMOS technology. In linear mode, the receiver achieves an in-band B\u3csub\u3e1dB\u3c/sub\u3eof -25.7 dBm at 1MHz offset with 34 dB gain setting. In nonlinear mode, blocker suppression is achieved by dynamically adapting a nonlinear transfer function according to the blocker amplitude. In the presence of a 0 to 9.6 dBm blocker, the receiver provides more than 38 dB of frequency-independent suppression, while consuming 8.7-15.7 mW in the RF stage. The maximum attainable blocker level exceeds P\u3csub\u3eDC\u3c/sub\u3e-5dB. The measured in-band B\u3csub\u3e1dB\u3c/sub\u3eis from -2.8 to 8 dBm at 1MHz offset for different settings. The measur...
Abstract—In this paper we propose a baseband noise-canceling receiver architecture to increase in-ba...
This paper presents a wideband blocker-tolerant RF front-end suitable for direct-ΔΣ-E-receivers. Blo...
In this paper the requirements and resulting costs for the digital hardware are discussed to steer a...
This paper presents a reconfigurable receiver with frequency-independent blocker suppression in a 40...
This paper presents a wideband frequency-translational resistive-feedback receiver (RX), operational...
This paper presents a 1.8GHz RF amplifier implemented in 140nm CMOS with frequency-independent block...
Cognitive radios (CRs) use “white spaces” in spectrum for communication. This requires front-end cir...
A 1.8GHz RF amplifier implemented in 0.14um CMOS with frequency-independent blocker suppression is p...
This paper presents a receiver front end with improved blocker handling implemented in a 65-nm CMOS ...
This paper presents a receiver front end with improved blocker handling implemented in a 65-nm CMOS ...
This paper presents a wideband blocker-tolerant Direct ΔΣ receiver (DDSR). Blockers are attenuated t...
This thesis targets cancellation of unwanted signals (blockers), one of the most difficult requireme...
| openaire: EC/H2020/704947/EU//ADVANTAG5Modern wideband receivers need to operate linearly in the p...
In this paper, a novel universal receiver baseband approach is introduced. The chain includes a post...
In this article, we propose a baseband noise-canceling receiver architecture to increase in-band lin...
Abstract—In this paper we propose a baseband noise-canceling receiver architecture to increase in-ba...
This paper presents a wideband blocker-tolerant RF front-end suitable for direct-ΔΣ-E-receivers. Blo...
In this paper the requirements and resulting costs for the digital hardware are discussed to steer a...
This paper presents a reconfigurable receiver with frequency-independent blocker suppression in a 40...
This paper presents a wideband frequency-translational resistive-feedback receiver (RX), operational...
This paper presents a 1.8GHz RF amplifier implemented in 140nm CMOS with frequency-independent block...
Cognitive radios (CRs) use “white spaces” in spectrum for communication. This requires front-end cir...
A 1.8GHz RF amplifier implemented in 0.14um CMOS with frequency-independent blocker suppression is p...
This paper presents a receiver front end with improved blocker handling implemented in a 65-nm CMOS ...
This paper presents a receiver front end with improved blocker handling implemented in a 65-nm CMOS ...
This paper presents a wideband blocker-tolerant Direct ΔΣ receiver (DDSR). Blockers are attenuated t...
This thesis targets cancellation of unwanted signals (blockers), one of the most difficult requireme...
| openaire: EC/H2020/704947/EU//ADVANTAG5Modern wideband receivers need to operate linearly in the p...
In this paper, a novel universal receiver baseband approach is introduced. The chain includes a post...
In this article, we propose a baseband noise-canceling receiver architecture to increase in-band lin...
Abstract—In this paper we propose a baseband noise-canceling receiver architecture to increase in-ba...
This paper presents a wideband blocker-tolerant RF front-end suitable for direct-ΔΣ-E-receivers. Blo...
In this paper the requirements and resulting costs for the digital hardware are discussed to steer a...