In this paper, we consider memory-mapping problems in High-Level Synthesis. We focus on the port mapping, bit-width mapping and word mapping, respectively. A 0-1 Integer Linear Programming (ILP) technique is used to solve the mapping problems, which synthesizes the source memory using one or more memory modules from a target memory library at a higher level. This method can not only perform bit-width mapping and word mapping, but it can also perform port mapping at the same time. Experimental results indicate that ILP approach is an effective method for memory reuse in high-level synthesis
ISBN : 1-58113-937-3We introduce a new approach to take into account the memory architecture and the...
Technology mapping is the task to transform a technology independent logic network into a mapped net...
This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area ...
Synthesizing designs for FPGA-based reconfigurable systems involves the task of mapping variables an...
One step in the synthesis for FPGA-based Reconfig-urable Computers (RCs) involves mapping the design...
We describe High-level Library Mapping (HLLM), a technique that permits reuse of complex RT-level da...
Field-programmable gate arrays (FPGAs) are integrated circuits (ICs) used for rapid prototyping and ...
We present High-level Library Mapping (HLLM), a technique that permits reuse of complex RT-level dat...
Abstract- High level synthesis. studies have produced many tools which enable us to design the proce...
The growing complexity of Field Programmable Gate Arrays (FPGA's) is leading to architectures with h...
Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) a...
ISBN 0-7695-2097-9We introduce a new approach to take into account the memory architecture and the m...
This paper presents a new approach to technology mapping for arbitrary technologies with single outp...
Systems handle more and more complex applications. Processing increases faster than storage capaciti...
High-level synthesis is a novel method to generate a RT-level hardware description automatically fro...
ISBN : 1-58113-937-3We introduce a new approach to take into account the memory architecture and the...
Technology mapping is the task to transform a technology independent logic network into a mapped net...
This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area ...
Synthesizing designs for FPGA-based reconfigurable systems involves the task of mapping variables an...
One step in the synthesis for FPGA-based Reconfig-urable Computers (RCs) involves mapping the design...
We describe High-level Library Mapping (HLLM), a technique that permits reuse of complex RT-level da...
Field-programmable gate arrays (FPGAs) are integrated circuits (ICs) used for rapid prototyping and ...
We present High-level Library Mapping (HLLM), a technique that permits reuse of complex RT-level dat...
Abstract- High level synthesis. studies have produced many tools which enable us to design the proce...
The growing complexity of Field Programmable Gate Arrays (FPGA's) is leading to architectures with h...
Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) a...
ISBN 0-7695-2097-9We introduce a new approach to take into account the memory architecture and the m...
This paper presents a new approach to technology mapping for arbitrary technologies with single outp...
Systems handle more and more complex applications. Processing increases faster than storage capaciti...
High-level synthesis is a novel method to generate a RT-level hardware description automatically fro...
ISBN : 1-58113-937-3We introduce a new approach to take into account the memory architecture and the...
Technology mapping is the task to transform a technology independent logic network into a mapped net...
This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area ...