The Hardware Accelerator SFDL/SCL

This paper presents a new multiprocessor architecture for modelling and simulation of digital circuits. To speed up the simulation process a special static algorithm for dividing modelled circuit components into equivalent classes (before the simulation starts) has been designed. In components of one class events will never appear at the same time. The number of equivalent classes is practically greater than or at least equal to the number of processors (n); therefore the classes are reduced into n groups. The main criteria in this process are: minimum data transmissions among processors and maximum usage of processors. All information (tables, programs) about elements of one group are stored in local memories of the processor assigned for that group. As the distribution into classes and groups is an NP-complete time consuming problem, 2 heuristic algorithms have been created for its solution. The first one is based on colouring of oriented graphs equivalent to modelled circuits, the other one uses matrix calculus. The results of simulation experiments proved that the designed multiprocessor architecture can speed up the simulation process by more than two orders in comparison with the classical simulation method