Design of a linear-in-dB power detector in 65nm CMOS technology

In this work, design and simula tion results of a linear-in-dB power detector are presented. The power detector can be used in integrated wireless communication devices for received or transmitted intermediate frequency (IF) signal power monitoring and control, local oscillator (LO) leakage detection. The whole detector block is composed of a mixer, amplifier and IF logarithmic amplifier to achieve linear-in-dB power detection. Design and simulation verification was performed using Cadence software pac kage. The propose d integrated circuit in 65 nm CMOS technology achieves a 74 dB dynamic range, while consuming 24 mW from 1,2 V power suppl