Design techniques for low-power low-noise CMOS capacitive-sensor readout circuits

In recent years, the demand for low-cost, high performance, and miniature sized MEMS capacitive inertial sensors (accelerometer/gyroscope) has been steadily increasing. Use MEMS capacitive accelerometer as an example, for high precision applications, the resolution needs to be in the μg range at the frequency of interest. These high performance sensors are now been used in numerous applications that require more demanding specifications. For instance, they found their use in active suspension, adaptive brakes, alarm systems, tilt control, vibration, shock measurements, platform stabilization, inertial measurement units, inertial navigation/guidance, machine control, microgravity measurements, seismology, geophysical sensing, oil-field applications, earthquake detection, tactical missiles, robotics and minimally invasive surgery. The precision in a micro-sensory system is limited by the CMOS electronic interfaces, due to the often higher electrical noise associated with the circuits. Additionally, with the growing popularity for portable devices such as cellular phones and tablets, power consumption also becomes an important factor. Therefore, the dissertation discusses and presents several circuit design techniques that improve important system parameters such as noise and power. Moreover, a design flow is provided at the end of the thesis to demonstrate a systematic approach to design the sensor interface circuits. Three major readout circuit blocks have been designed, built, and tested. The first interface uses a circuit technique such that the overall system is insensitive to parasitic capacitances from the sensing nodes. Moreover, a calibration scheme is used to remove DC offset caused by sensor capacitance mismatch. The second interface uses two circuit design techniques called correlated level shifting (CLS) and chopper stabilization (CS) to reduce the noise and the finite gain error from the operational amplifier (op amp), thereby improving both the noise and power performance of the system. The final interface utilizes a modified CLS technique such that it also serves as a noise and power improving mechanism. The first two readout circuits have been tested and measured experimentally, while the third readout circuit is verified via post-layout simulation.Applied Science, Faculty ofElectrical and Computer Engineering, Department ofGraduat