Efficient power and data converter circuits for RFID applications

The basic concept of radio-frequency identification (RFID) as a means of wireless identification of physical objects has existed for over half a century. However, the technology became economically feasible during the mid-90s mainly due to proliferation of low-cost integrated circuits. Since its emergence, RFID technology has gained extensive attraction and has been used in numerous industrial applications. To facilitate widespread deployment, RFID tags as the backbone of such identification systems have to fulfil two general requirements, namely, low power consumption and small form factor. In this thesis, with an emphasis on power and area efficient architectures, efficient data and power converters as the two major building blocks of sensor-enabled RFID tags are investigated. In the context of data conversion, by using two low-power analog buffers instead of the conventional binary weighted capacitive array, a low-power 8-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with an area efficient digital-to-analog converter (DAC) architecture is proposed. Furthermore, time-mode ADC as an alternative area and power-efficient structure is discussed and a highly linear, wide-input-range voltage-to-time converter (VTC) is presented and experimentally evaluated. In the context of efficient power converters, through optimizing the bias voltage of the gate of switching transistors in a conventional differential rectifier, three high-efficiency RF rectifier architectures, namely, gate-boosted, auxiliary-cell biased, and quasi-floating-gate (QFG)-biased rectifiers are proposed. Furthermore, through dynamically adjusting the input capacitance, a dual-band matching approach for RF rectifiers is presented. The proposed QFG-biased rectifier is incorporated and analyzed in a wake-up radio front-end. Also, backscattering method as a power efficient scheme during the transmit mode is studied in the context of biomedical implants. Furthermore, based on the techniques developed for enhancing the efficiency of the rectifier, an ultra-low-power complementary metal-oxide-semiconductor ( CMOS ) voltage-controlled ring oscillator architecture is proposed. The proposed building blocks and systems, namely, ADC, rectifiers, wake-up radio structure, and voltage-controlled ring-oscillator architecture are designed in a 0.13-µm CMOS technology and their performances are verified through post-layout simulation and/or measurement results.Applied Science, Faculty ofElectrical and Computer Engineering, Department ofGraduat