On the design of low-voltage power-efficient CMOS active down-conversion mixers

The scaling of CMOS technologies has a great impact on analog and radio-frequency (RF) circuit design. In particular, as technology advances the available voltage headroom is decreased due to the use of lower supply voltage. In addition to design challenges due to the headroom limitation, the power consumption is also becoming more important, in particular, in wireless communication applications and portable devices. In this work, we investigate several design techniques for achieving ultra-low-voltage (< 0.5 V), ultra-low-power (< 500 µW), and ultra-wideband (DC to 8 GHz) wireless receiver building blocks with a specific focus on the active CMOS mixers. Mixers are important building blocks of almost all modern transceivers and they are primarily used for frequency translation. In this work, we briefly review many state-of-the-art design techniques, discuss the advantages and drawbacks of currently used methods, and then we introduce design techniques to improve performances of different receiver building blocks, namely, mixers and LNAs. As a proof-of-concept three different RF active CMOS mixers are designed, have been fabricated in 0.13-µm and 90-nm CMOS processes, and are successfully tested. We have also proposed a linearization method, which is specifically applicable to mixers and low-noise-amplifiers (LNAs). A proof-of-concept circuit for the proposed linearization technique is also designed and implemented in a 0.13-µm CMOS process and is successfully tested.Applied Science, Faculty ofElectrical and Computer Engineering, Department ofGraduat