This work describes the design, construction, and testing of a digital-to-analog function generator and multiplier for analog computation and non-linear system simulation. The unit consists of two separate channels each of which is fed by a punched paper tape. Functions (of time) are represented on the tapes in binary code and are read into the machine photoelectrically. In one channel, voltage sources of constant value but of either polarity are switched into the parallel branches of a ladder network in accordance with the incoming digital information. As a result of the particular choice of resistor values in the ladder network the voltage at one end of the resistive network is proportional to the binary number signified by the polarity ...