Design of a serialized link for on-chip global communication

On-chip global communication is required for data and control transfers across various modules on the chip and determines the performance of the integrated circuit in current technology generation. A particularly difficult challenge at the present time is the routing complexity and congestion of parallel buses that span large distances on the chip. This thesis presents the design of an on-chip serialized link for replacing a parallel bus. The serial channel uses a wave-pipelined signaling scheme which provides high data rates to compensate for the loss of parallelism. A serializer-deserializer (SERDES) transceiver is investigated to determine the required number of wires in the serial channel based on interconnect bandwidth and design overhead. Further, the robustness of the SERDES technique is studied in the presence of on-chip variations. A technique for reducing the energy consumption on the serial channel by lowering the average switching activity is also proposed. Using our design technique, a 32-bit wide parallel bus operating at a frequency of 1Ghz in 90nm CMOS technology can be replaced by a serial channel consisting of 4 interconnects. Considering overhead due to the SERDES transceiver itself, the number of interconnects required in the serial channel increases to 8. Further, the intra-die variation forces the required number of interconnects to 16. This thesis also demonstrates that the energy of a serialized link can be reduced by up to 40% if there is prior knowledge of the data to be transmitted on the bus.Applied Science, Faculty ofElectrical and Computer Engineering, Department ofGraduat