Structured logic arrays as an alternative to standard cell ASIC

In the deep submicron (DSM) era, design rules have become increasingly more stringent and have favoured the more structured architectures. The design methods using standard cell ASICs (SC-ASIC) produce randomly placed gates and interconnects. Beside reduced yield, they also suffer from high testing cost, even with the most advanced builtin self-test methods. These shortfalls motivate us to search for an alternative architecture in the structured logic arrays. First, we will explore the available structured logic arrays and their potentials as alternatives to SC-ASIC architecture. Then we will focus on programmable logic arrays to explore their potential when competing for speed and area with SC-ASIC. We have investigated the critical path delay for clock-delayed PLA and suggested equations for quick calculation o f its capacitive loads and delay. We have also introduced equations to calculate their area using technology-independent parameters. This would help the front-end CAD tools in partitioning and architecture decision-making before committing to a specific technology. We found that circuits with higher than 200 product terms have slower PLA implementations than SC-ASIC. They also tend to take more than 10 times the area. Furthermore, we have introduced logical effort as a simple method for gate sizing and optimization o f the PLA' s critical path delay. Finally, we have introduced methods to subdivide the slower PLAs in order to improve the overall circuit timing. We also found that by dividing a circuit to two PLAs we can cut its delay by half and keep the increase in area minimal.Applied Science, Faculty ofElectrical and Computer Engineering, Department ofGraduat