Design, layout and placement of on-chip decoupling capacitors in IP blocks

In today's deep submicron technologies, a number of new signal integrity issues have arisen due to increased resistance, coupling capacitance and inductance in the metal interconnect. One of the main concerns is power supply noise in the form of IR drop and Ldi/dt effects as clock frequency continues to increase. As supply voltages scale down with technology, and the level of current and its rate of change increases, the noise levels on the supply are increasing to detrimental effect. Power supply noise can increase the delay of gates and even cause them to function improperly. This thesis addresses the use of standard-cell decoupling capacitors (decaps) to reduce power supply noise in IP (intellectual property) blocks that are designed using standard cell layout tools. First, we study the performance of decaps, implemented using MOS transistors, as a function of frequency. A number of observations are made, both qualitatively and quantitatively, about the behaviour of NMOS and PMOS transistors when used as decoupling capacitors. In addition, a number of equations are derived to characterize the frequency and time-domain behaviour of decaps. Using these equations and SPICE simulations, a number of recommendations are made as to how decaps should be laid out. The issues of where to place decaps and how much to place is also addressed using a commercial power grid analysis tool. General design guidelines are developed based on the results to keep noise below the budgeted amount during the layout of an IP block.Applied Science, Faculty ofElectrical and Computer Engineering, Department ofGraduat