Non-rectangular embedded programmable logic cores

As System-on-a-Chip (SoC) design enters into mainstream usage, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. These cores are like any other intellectual property (IP) in the SoC design methodology, except that their function can be changed after fabrication. In many cases, nonrectangular programmable logic cores are required, either to better mesh with the other IP cores, or because of I/O constraints. However, most CAD algorithm and programmable logic architecture research targets standalone field programmable gate arrays (FPGA's), which are invariably square or rectangular. In this thesis, we enable researchers to evaluate nonrectangular programmable logic cores by a novel specification method and an enhanced CAD tool. We also show that existing placement and routing algorithms do not work well when targeting non-rectangular programmable logic cores, and we present enhancements to existing placement and routing algorithms that allow the algorithms to better target these cores. It is shown that the new algorithms lead to a 12% critical path improvement for "U"- shaped cores, and a 4% critical path improvement for "0"-shaped cores. The density and speed penalty for using these non-rectangular cores is significant, compared to square cores, however, we show that the penalty would be significantly larger if the original algorithms were used.Applied Science, Faculty ofElectrical and Computer Engineering, Department ofGraduat