A multimedia co-processor architecture for real-time video coding

Digital video evolves rapidly in the exciting multimedia industry, but also presents new challenges to system designers. As it is too expensive to store the massive raw digital video streams and to transport them over any transmission channels, researchers developed digital video encoding techniques that significantly reduce the size of digital video data while maintaining the picture quality. But such encoding techniques require tremendous processing power especially for operations including motion estimation, discrete cosine transform (DCT) and quantization. This thesis presents a low-cost but efficient and flexible architecture of an embedded programmable multimedia co-processor optimized for motion estimation as well as a combined DCT and quantization (QDCT) algorithm. To meet the low cost constraint, we minimize the number of hardware resources and maximize the hardware utilization by optimized scheduling. Unlike DSPs and media processors, this architecture has a much simpler controller with a small instruction set. It adopts a hybrid controller design of mixing user programmable instructions and hard-wired micro-codes. User instructions provide flexibility to the implementation of the motion estimation algorithm for various coding specifications and future changes in the standard. Micro-codes are used to execute the low-level computation intensive routines. It shows that micro-codes can execute the kernel loops in those routines very efficiently with optimized scheduling on the specialized processing engine. Such processing engine features a parallel architecture with specialized functional units, supporting SIMD executions. Overall, the multimedia co-processor is a tightly-coupled system consisted of a specialized processing engine, an efficient memory architecture and a flexible controller all working in a coherent manner.Applied Science, Faculty ofElectrical and Computer Engineering, Department ofGraduat