Architecture of a high speed JBIG processing engine

The high volume of traffic in facsimile transmissions has lead to demands for high-speed image processors to use in dedicated multi-channel fax devices. Image processors in these devices must provide a high throughput of data as well as the ability to easily switch between processing of different images. In this thesis, the architecture of an image processing engine for the encoding and decoding o f images based on the Joint Bi-level Image Group (JBIG) standard is proposed. When used in conjunction of another processing engine for the coding of modified Huffman (MH), modified Read (MR) and modified modified Read (MMR) images, the engine is capable of compressing and converting between these facsimile standards on the fly at a high data rate. Another application of the JBIG engine is in the controller of digital printing or copying devices where image compression can effectively reduce memory usage. For efficient implementation of the standard, the JBIG facsimile standard is analyzed to exploit parallelisms in the algorithm. The proposed JBIG engine utilizes a simple pipelined architecture to achieve a throughput of close to 1 pixel per clock cycle. Synthesis results show that the JBIG engine can run at a clock rate of 50 MHz on an Altera Flex 10KE family -1 speed rated programmable logic device.Applied Science, Faculty ofElectrical and Computer Engineering, Department ofGraduat