Product term mode embedded memory arrays : algorithms and architectures

Field-Programmable Gate Arrays (FPGAs) are integrated circuits that can be programmed to implement virtually any digital circuit. Due to the ease with which a user can implement a circuit, FPGAs have become a low-cost, fast-turnaround time alternative to more traditional implementation technologies such as mask-programmed gate arrays and application-specific integrated circuits (ASICs). However, one of the major pitfalls of FPGAs is the area and speed penalty inherent in the technology. In order to help "bridge the gap" between FPGAs and ASICs, intelligent computer-aided design (CAD) tools that use the FPGA as efficiently as possible are needed. In this thesis, we focus on mapping logic to the on-chip memory arrays. In particular, our focus is on the architecture of the product-term mode memory arrays, and the CAD algorithms that target those architectures. First, we focus on an intelligent technology mapping algorithm that maps a circuit to product term mode memory arrays. We show that the algorithm can pack 22.8% more logic blocks into product term mode memory arrays over using conventional memory arrays alone. Second, we focus on the architecture of the product term mode memory array itself, and present several architectural enhancements for increasing the efficiency of the memory array in implementing logic.Applied Science, Faculty ofElectrical and Computer Engineering, Department ofGraduat