A tool for formal verification of DSP assembly language programs

Formal verification has, in recent years, become widely used in the design and implementation of large integrated circuits, but its use in general software verification has been more limited. We have developed a new technique to verify assembly code for digital signal processors (DSPs) that makes significant steps into the realm of software verification and serves as a good building block for future verification efforts. In order to demonstrate the applicability of our approach, which takes inspiration from successful techniques applied in hardware verification, we have implemented a prototype tool to verify assembly code for a Fujitsu DSP chip. The approach we have created is based on symbolic simulation with uninterpreted functions and control flow analysis. DSP assembly language programs are an attractive target for formal verification. On one hand, DSP assembly language programs must often be modified for size and speed constraints which requires that the code be optimized by taking advantage of the idiosyncrasies of the chip. This optimization can make even small programs hard to reason about and debug. On the other hand, verification of optimized versus unoptimized versions of the same program can be simplified by exploiting the similarities between the two. This combination produces an application domain that is simultaneously challenging yet tractable. This thesis describes our verification approach and how we were able to successfully implement a prototype tool.Science, Faculty ofComputer Science, Department ofGraduat