Design and implementation of a code-phase-shift keying spread spectrum receiver employing a FPGA baseband decoder

Code-phase-shift-keying (CPSK) is a novel direct sequence spread spectrum (DS/SS) signaling technique aimed at improving the data throughput of a DS/SS system without the lost of processing gain. To further evaluate its practical performance, a CPSK modem needs to be designed and implemented. This thesis addresses the above objective, concentrating on the digital receiver. The CPSK receiver consists of three major modules, the IF demodulator, the CPSK decoder, and the PC interface. As with other DS/SS systems, carrier phase and PN code phase synchronization are the two most important issues to be addressed in the design of the CPSK receiver. Carrier phase synchronization is solved by employing a Costas loop in the demodulator to lock the carrier phase and limit the phase uncertainty to either 0 or 180 degree. The uncertainty is then completely resolved by using double thresholds in the CPSK decoder. A modified double dwell serial search scheme with a tracking loop is employed in the CPSK decoder to achieve PN code phase synchronization. Furthermore, to add the flexibility in decoding data with different symbol size and PN code length, a re-programmable Xilinx 4010 FPGA chip is employed to build the decoder. To evaluate the performance of the receiver, extensive symbol-error-rate (SER) measurements In the presence of additive white Gaussian noise and jamming from another CPSK transmitter are conducted, and the resulting bit error rate (BER), versus signal to noise ratio curves are compared with those, of an ideal receiver. Results show that there were 0.25 to 0.85 dB BER degradation when the carriers of both the transmitter and receiver are perfectly synchronized, and a further ldB degradation when the Costas loop is employed. Jamming from another transmitter results in substantial degradations in the BER performance in a noisy environment. The scalability of the CPSK decoder is also studied based on the reconfigurability of the XC4000 FPGA family. The possible symbol size / PN code length combinations of the decoder that can be fitted into the FPGA chip are discussed and the modifications needed for each major component of the decoder are outlined. Finally, the maximum throughput possible with the FPGAs is addressed.Applied Science, Faculty ofElectrical and Computer Engineering, Department ofGraduat