With the increasing complexity of modern VLSI circuits, achieving high quality built-in self-test requires monitoring an increasingly large number of internal nodes. Due to the limitations in observing large numbers of nodes, it has become increasingly necessary to compact the output from a large number of lines to a small number of lines in a process known as space compaction. In the past, space compaction has usually been performed by circuit-independent compactors, such as the popular parity function. Recently, a class of circuit-specific space compactors, known as programmable space compactors (PSCs), has been proposed. A PSC is a highly effective space compactor tailored for a specific circuit under test (CUT) subjected to a sp...
Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem ca...
Current paper presents a new technique for static compaction of sequential circuit tests that are di...
This paper presents two new algorithms, Redundant Vector Elimination (RVE) and Essential Fault Reduc...
With the increasing complexity of modern VLSI circuits, achieving high quality built-in self-test r...
A new space compaction technique for built-in self-testing (BIST) of VLSI circuits using compact tes...
This technical report is prepared to record the preliminary work carried out in beginning a research...
Built-in self-testing (BIST) is a design process that provides the capability of solving many of the...
Abstract One method for compacting executable computer code is to replace commonly repeated sequence...
The test compaction is one of most important requirement regarding the large scale integration (LSI)...
The present thesis deals with the general problem of designing and analyzing efficient space compres...
Built-in self testing (BIST) offers an attractive solution to the problem of testing complex VLSI ci...
This thesis deals with response compaction techniques of BIST of VLSI circuits which translates into...
The problem of compacting a set of test sequences for sequential circuits is modeled here with the h...
[[abstract]]Test set compaction for combinational circuits is studied in this paper. Two active comp...
Abstract—In most of existing approaches, the reorganization of test vector sequence and reordering s...
Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem ca...
Current paper presents a new technique for static compaction of sequential circuit tests that are di...
This paper presents two new algorithms, Redundant Vector Elimination (RVE) and Essential Fault Reduc...
With the increasing complexity of modern VLSI circuits, achieving high quality built-in self-test r...
A new space compaction technique for built-in self-testing (BIST) of VLSI circuits using compact tes...
This technical report is prepared to record the preliminary work carried out in beginning a research...
Built-in self-testing (BIST) is a design process that provides the capability of solving many of the...
Abstract One method for compacting executable computer code is to replace commonly repeated sequence...
The test compaction is one of most important requirement regarding the large scale integration (LSI)...
The present thesis deals with the general problem of designing and analyzing efficient space compres...
Built-in self testing (BIST) offers an attractive solution to the problem of testing complex VLSI ci...
This thesis deals with response compaction techniques of BIST of VLSI circuits which translates into...
The problem of compacting a set of test sequences for sequential circuits is modeled here with the h...
[[abstract]]Test set compaction for combinational circuits is studied in this paper. Two active comp...
Abstract—In most of existing approaches, the reorganization of test vector sequence and reordering s...
Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem ca...
Current paper presents a new technique for static compaction of sequential circuit tests that are di...
This paper presents two new algorithms, Redundant Vector Elimination (RVE) and Essential Fault Reduc...