Adaptive clock recovery and jitter control in ATM networks

Transporting continuous bit rate (CBR) or real-time periodic traffic is one of the major services that ATM-based B-ISDN technology is promising to provide. This service requires the receiver to preserve the original inter-cell spacing. However, statistical multiplexing and buffering in the ATM transport networks can introduce significant jitter in the inter-arrival period of the cell stream, thus degrading the quality, of the cell play-back at the receiver. An additional complication in plesiochronous networks is the absence of the transmitter clock frequency at the receiver. Therefore, the receiver must be capable of extracting the frequency of the transmitter clock and removing the jitter from the arriving cell stream. This thesis provides a thorough treatment of the clock recovery and jitter removal problems for CBR traffic in ATM networks, and proposes a new practical design of a receiver unit for handling multirate CBR traffic. The design proposed complies with the ATM standards. Our design employs a number of control parameters that can be varied to optimize the operation of the receiver and to provide high adaptability to rapidly changing input cell traffic. The proposed scheme is based on monitoring the fluctuation in the receiver buffer occupancy to derive a jitter free receiver clock. The hardware design has been specified and simulated extensively using VHDL (a hardware description language), and the simulation results show that our design is robust and very effective in removing cell delay jitter and restoring the original CBR stream.Applied Science, Faculty ofElectrical and Computer Engineering, Department ofGraduat