Design of Power-efficient Analog-to-digital Converters and a Mixed-mode low Drop-out Regulator

The increasing demand of portable electronic devices, such as cell phones, biomedical products, smart devices, etc, has been witnessed in recent years. These devices have limited power due to their battery life. Therefore, power-efficient researches and designs for IC chips used in the portable devices become more popular. One hot topic is about a power-efficient high resolution, wide bandwidth analog-to-digital converter (ADC) design. The ADC block is one of the key building blocks in a wireless communication system. The ADC is employed to process baseband signals after a mixer and filters. It converts analog signals into digital format for microprocessors/controllers. Hence, the power consumption of the ADC is important since the ADC is one of the most frequently used building blocks in the wireless communication system. Another widely used blocks are on-chip regulators. They regulate the supply voltages for different parts/cores on a microchip. Nowadays, many applications require different building blocks switching frequently between sleeping and operation modes. In this case, power-efficient on-chip regulators with fast transient response are demanded. This research consists of three projects. All projects are about power-efficient analog and mixed-signal circuits design. The first research is a 13-bit 260MS/s pipeline ADC using a currentmode (CM) multiplying digital-to-analog converter (MDAC) with a current-reuse technique and interstage gain calibrations. In this pipeline ADC, the CM MDAC architecture is utilized to replace the conventional switch-capacitor (SC) architecture. The CM MDAC employs an operational transconductance amplifier (OTA) converting the voltage input signal into a current output signal. At the same time, the sub-ADC in the CM MDAC solves N bits which drives an N-bit currentsteering DAC. The current residue signal is generated at the output of the DAC and the OTA. Then, a transimpedance amplifier (TIA) is utilized to convert the current residue back to a voltage output for next pipeline stages. To overcome interstage gain errors due to variations, the errors are calibrated in digital domain. Finally, the work achieves a 68.1/66.3 dB signal-to-noise-anddistortion ratio (SNDR) and 82.3/78.2 dB spurious free dynamic range (SFDR) for a sinusoidal inputs at 4.1736/123.129 MHz. The total power consumption for the ADC is around 15.38 mW. The Walden figure-of-merit (FoM) is 28.3 fJ/conv-step with low frequency input. The chip was implemented by TSMC 40nm technology. The phototype occupies around 0.28 mm2 . The second project is a system-level design of a time-interleaved ADC with digital background calibrations. In this project, a 4-channel time-interleaved ADC with one additional ADC for calibration is proposed. The calibration algorithm matches the 4-channel ADCs’ outputs with the additional ADC by adjusting their gains, offsets and sampling clock phases. These three types of mismatches and skews are considered as the main errors for a high-speed time-interleaved architecture. The algorithm is implemented and functionally verified by using a field programmable gate array (FPGA) and commercial ADCs (ADS4126). In the last project, a 245mA digitally-assisted dual-loop low dropout (LDO) regulator is proposed and implemented in a TSMC40nm process. The purposed digitally-assisted loop is to speed up the transient response of large load variations. In this way, the digital loop maintains the loop speed of the LDO using dynamic current instead of large DC current. However, the digital loop has finite resolution leading to a current quantization error at the output. One of pass transistors in the LDO is turned on/off periodically in a steady state condition. In order to solve the issue, the analog loop is utilized for the steady state condition. It regulates small load changes. The digital loop is activated for tracking large load steps only. The digitally-assisted dual-loop LDO achieves 245mA maximum load current. The power supply rejection (PSR) is -48 dB at low frequency and -43 dB at 1 MHz for a 240 mA load respectively. The LDO with low load current still shows -34 dB rejection at 1 MHz. The quiescent current is approximate to 300 µA. The measured load transient tests indicate that the LDO has 71 mV/37 mV voltage droops under a rising/falling edge of the maximum current step. The FoM based on the results is 7.4 ps which is highly competitive with recently published LDO designs