An Improved Current Mirror Cell

A new configuration for the design of a current mirror is presented. The proposed configuration eliminates the DC matching error caused by the difference between drain-to-source voltages of both input and output transistors. The circuit can be used to enhance the accuracy of analog circuits for current levels from 0 to few hundreds microamperes The proposed configuration was verified by HSPICE simulator level 49 in 0.8m CMOS process technology. Simulation results show that DC matching error is substantially reduced compared to the cascade configuratio