© 2019 The Royal Society of Chemistry. The continuation of CMOS scaling leads to the necessity of replacing Cu as an interconnect material with a metal with lower resistivity and better reliability performance. At the same time, significant technological improvements are required to mitigate the pattern overlay requirements when forming multilevel structures with a half-pitch below 10 nm. Area-selective deposition (ASD) offers an elegant way to enable self-alignment of multilevel structures. However, defectivity is a typical bottleneck of ASD integration. This work explores the selective electroless deposition (ELD) of Co as a replacement of Cu as an interconnect metal. The selective metallization process is promoted by the selective place...