Digital Enhancement of SAR ADCs

Digital data processing has become deeply integrated in our lives. We see the prefix 'smart' attached to an increasingly varied set of devices, from phones and TV's to cars, homes and even washing machines. These devices are full of sensors that allow them to interact with the real, analog world. Analog-to-Digital Converters (ADCs) are one of the fundamental blocks that allow digital devices to process analog information. As modern applications require ADCs to become faster, more accurate and power efficient, physical limitations start to negatively affect their performance. Luckily, data converters can benefit from the integration with increasingly intelligent digital devices by allowing errors in the conversion to be corrected in the digital domain. Successive Approximation Register (SAR) ADCs are one of the most popular ADC architectures used nowadays. SAR ADCs are well suited to CMOS integration, as they use mostly digital components. They offer a good compromise between sampling rate, power, dynamic range and die area. Their performance is however limited by mismatch in their internal components, and their conversion speed is not very high among the different ADC architectures due to their iterative nature. By combining SAR converters with techniques like pipelining and time-interleaving, it is possible to design fast converters with high resolution, as long as the non-linearities in such hybrid converters are successfully countered. The first part of this work focuses on developing power-efficient, on-chip digital background calibration schemes that can improve the performance of SAR ADCs, as well as that of more complex architectures that use SAR ADCs as a main building block. Current state of the art digital calibration algorithms either focus on the most significant source of distortion, or if they attack multiple non-idealities, do so one by one. One of the objectives of this work is to develop a joint scheme for the calibration of multiple ADC non-idealities. Through a novel calibration scheme and silicon proven chips we demonstrate that area and power efficient on-line calibration can be efficiently implemented on chip for pipelined and time-interleaved SAR converters. As devices and sensors become more integrated, the amount of raw data to quantize and process in integrated multi-sensor systems grows at a staggering rate. The second part of this work focuses on developing smarter, more efficient converters that not only translate the analog signal to the digital domain, but also simultaneously extract relevant information. This is achieved through a resource-efficient configurable ADC that jointly converts and compresses the signal, allowing for savings in the digital backend.status: publishe