Automatic Defect-Oriented Test Generation for Analog and Mixed-Signal Integrated Circuits

The fabrication process of modern integrated circuits (ICs) is not perfect and the resulting manufacturing yield never reaches 100%. Therefore, manufactured ICs have to be tested in order to filter out the defective chips before they reach the electronic market. Therefore, solutions are needed to simultaneously improve the test coverages and reduce the time required to design these tests. In this research, we develop a framework based on the defect-oriented methodology. By modeling the physical defects which can occur in an IC, the effects a defective circuit can be simulated. Based on this simulated behaviors, structural tests can be generated i.e. tests targeting the defects of the circuit instead of the functionality of the circuit. On the one hand, an automatic test signal generation method is developed by partitioning the considered circuits into sub-circuits. Then, the Kirchhoff's current law describing the interactions of these sub-circuits are solved with interval analysis. On the other hand, a set of building blocks enhancing the observability and controllability of the circuits are studied in order to automate the injection of test hardware into the circuit. As a result, the combination of the test signal generation and test hardware generation forms a framework enabling the automatic test generation for the targeted IC.status: publishe