mm-Wave Building Blocks for Future 5G Transceivers in Deep-scaled CMOS

CMOS is the technology of choice for mass production digital circuits, key to achieve low cost and low power circuits. CMOS will also be a key enabler for future 5th generation (5G) cellular systems. Together with the classical requirements of higher data rate and spectrum efficiency, connection density, area traffic capacity and latency are becoming key features. These requirements are fundamental to improve the user experience, core added value of the IoT. Moreover, these specifications should be met while achieving 100x better network efficiency. Together with this win-win relationship between lower cost and lower power, at each technology node the MOS transistors get faster. Digital processors therefore enjoy the full benefit of technology scaling, but this is not always the case for high speed analog design. Despite the aggressive technology scaling and relative improve ft, severe challenges are posed on the high frequency analog front-end. The three major challenges that an analog designer faces at mm-Wave frequencies are the following. At higher frequency the transconductor shows (1) lower gain and (2) higher noise. Moreover, (3) the effect of the low level metal connections becomes dominant, the quality factor of capacitors gets worse and inductors do not improve. This research explores novel design techniques to meet the specifications on large bandwidth and high frequency of operation without jeopardizing noise and efficiency. The key high speed building blocks that limits the performance of PLLs, receivers and transmitters are investigated, resulting in beyond state-of-the-art measured results.status: publishe