© 2015 IEEE. Replacement of sacrificial template by ultralow-k dielectric was studied as an alternative integration approach for Cu/low-k interconnect. Metallization structure was first formed by patterning a template material. After template removal, a spin-on porous low-k was deposited on the metal lines. Then, planarization of the excess low-k was performed by CMP. The proposed approach does solve the two major challenges in conventional Cu/low-k damascene integration approach: low-k plasma damage and metal penetration during barrier deposition on porous structures.status: publishe
Advanced interconnect technologies require the continuous development of reliable low-k dielectric m...
Plasma induced damage of ultra low-k (ULK) dielectrics is a common phenomenon in BEOL interconnects....
Since the application of silicon materials in electronic devices in the 1950s, microprocessors are c...
© 2015 AIP Publishing LLC. Cu/low-k integration by conventional damascene approach is becoming incre...
This paper reports about examinations on mechanical integrity improvement which were done to enable ...
Dielectric stacks containing porous low-k materials were investigated regarding their ability to pas...
Integration of dielectrics with increased porosity is required to reduce the capacitance of intercon...
Nowadays the implementation of copper and low k material into IC fabrication is a serious issue for ...
The Cu/low-k damascene process was introduced to alleviate the increase in the RC delay of Al/SiO2 i...
Downlooften silicon nitride or silicon oxide, has a higher dielectric constant (high-k, 4.0 < k &...
On-chip integration of passive devices like inductors, capacitors, resistors, transmission lines etc...
The solution to the problem of increased resistance-capacitance (RC) delay in the present day ULSI i...
An alternative indirect integration regime of porous low-k materials was investigated. Based on a si...
As VLSI technologies advance, they closely follow Moore’s Law where devices are scaled down to small...
As Cu damascene process and low dielectric constant material (low-k) are introduced into back-end of...
Advanced interconnect technologies require the continuous development of reliable low-k dielectric m...
Plasma induced damage of ultra low-k (ULK) dielectrics is a common phenomenon in BEOL interconnects....
Since the application of silicon materials in electronic devices in the 1950s, microprocessors are c...
© 2015 AIP Publishing LLC. Cu/low-k integration by conventional damascene approach is becoming incre...
This paper reports about examinations on mechanical integrity improvement which were done to enable ...
Dielectric stacks containing porous low-k materials were investigated regarding their ability to pas...
Integration of dielectrics with increased porosity is required to reduce the capacitance of intercon...
Nowadays the implementation of copper and low k material into IC fabrication is a serious issue for ...
The Cu/low-k damascene process was introduced to alleviate the increase in the RC delay of Al/SiO2 i...
Downlooften silicon nitride or silicon oxide, has a higher dielectric constant (high-k, 4.0 < k &...
On-chip integration of passive devices like inductors, capacitors, resistors, transmission lines etc...
The solution to the problem of increased resistance-capacitance (RC) delay in the present day ULSI i...
An alternative indirect integration regime of porous low-k materials was investigated. Based on a si...
As VLSI technologies advance, they closely follow Moore’s Law where devices are scaled down to small...
As Cu damascene process and low dielectric constant material (low-k) are introduced into back-end of...
Advanced interconnect technologies require the continuous development of reliable low-k dielectric m...
Plasma induced damage of ultra low-k (ULK) dielectrics is a common phenomenon in BEOL interconnects....
Since the application of silicon materials in electronic devices in the 1950s, microprocessors are c...