Wide-bandwidth Power-efficient VCO-based Delta-Sigma Analog-to-Digital Converters

Analog designers have to face large challenges arising from CMOS technology scaling. The voltage dynamic range is greatly reduced in nanometer CMOS processes, making previously successful and mature analog building blocks no longer practical. One approach to overcome this challenge is to process a signal in the time domain. The implementation of circuits in the time domain immediately takes advantage again of the technology scaling. Contrary to the amplitude resolution, the time resolution is continuously improving with scaling due to the reduction of the gate delay, despite the reduction of the supply voltage. This work focuses on power-efficient wide-bandwidth time-domain Delata-Sigma ADC designs as needed for future wireless communication applications. As a popular time-domain ADC candidate, the VCO-based ADC is motivated and investigated in this work. To address the VCO nonlinearity problem, which is the main performance bottleneck of this kind of ADC, novel power-efficient solutions are proposed in this work both at architecture level and circuit level. A nonlinearity-cancellation technique in a 0-DelataSigma MASH structure is adopted. A 0-2 MASH VCO-based Delata-Sigma ADC prototype implemented in 40-nm CMOS confirms the theoretical analysis and achieves a SNDR of 66.8 dB over a 40-MHz BW, consuming only 4.98 mW. By taking full advantage of the low-power VCO-based circuit and overcoming its inherent nonlinearity problem, the FoM of the state-of-art high-bandwidth Delata-Sigma ADCs has been extended to 166 dB (SNDR+10log(BW/Power)). In addition, since technology scaling has greatly decreased the power dissipation of digital circuits, it is also beneficial to transfer even more analog building blocks to the digital domain to reduce even further the power consumption. In this work, a VCO is proposed to replace the power-hungry analog integrator in the traditional Delata-Sigma ADC topology. A VCO theoretically has an infinite DC gain, which is power efficient and independent from the supply voltage. In this work, we report a 0-2 MASH Delata-Sigma ADC in 40-nm CMOS with fully-VCO-based integrator and quantizers, without any analog integrators. 74-dB SFDR and a FoM of 162 dB over a 40-MHz bandwidth have been achieved in the measurements. Finally, there is an increasing need in recent years for energy harvesting circuits to scavenge ambient energy for autonomous applications. The second part of this PhD work focuses on exploring fully integrated rectenna-based energy harvesting technology, at both the optical and mm-wave bands. Fundamental enabling research necessary for nano-antenna-based rectenna design and its realization for solar energy harvesting is discussed. An on-chip antenna with embedded low-pass filter operating at 160-GHz frequency is designed. Also, a CMOS rectifier operating at 160-GHz frequency is implemented in 40-nm standard CMOS technology. This is the highest operating frequency ever reported for a rectenna.Abstract List of Abbreviations Content List of Figures List of Tables 1 Introduction 1.1 Motivation 1.2 Research objective and contributions 1.3 Thesis organization 2 Overview of Delta-Sigma ADCs 2.1 ADC basics: sampling and quantization 2.2 ADC specifications 2.3 ADC architectures 2.4 Principle of DS ADCs: oversampling and noise shaping 2.4.1 Oversampling 2.4.2 Noise shaping 2.4.3 Higher-order DS modulator 2.5 Multi-stage DS modulators 2.5.1 The DS-0 and 0-DS MASH structures 2.6 Conclusions 3 VCO-based ADCs: the basics 3.1 Motivation: time-domain quantization 3.2 Voltage-to-time converter 3.2.1 Duty-cycle modulation 3.2.2 Voltage-controlled oscillator 3.3 Time-to-digital converter 3.3.1 Delay-line-based TDC 3.3.2 Oscillator-based TDC 3.4 Time-domain ADC 3.5 Performance anaysis of the VCO-based ADC 3.5.1 Phase-domain quantization 3.5.2 VCO nonlinearity 3.5.3 VCO phase noise 3.5.4 Clock jitter 3.5.5 Delay cells mismatch 3.6 Implementations of VCO-based ADCs 3.6.1 Nonlinearity suppressed by loop gain 3.6.2 Nonlinearity compensated by calibration 3.6.3 Nonlinearity mitigated by DCM precoding 3.6.4 Nonlinearity mitigated by reduced input swing 3.6.5 Nonlinearity cancelled in a cascaded structure 3.7 Conclusions 4 VCO-based 0-DS MASH ADCs 4.1 Introduction 4.2 Architecture analysis of the 0-DS MASH VCO-based ADC 4.2.1 0-DS MASH VCO-based ADC 4.2.2 Nonlinearity-cancellation robustness against PVT variations 4.3 Design example: a 0-2 MASH VCO-based DS ADC 4.3.1 System architecture 4.3.2 Delay matching technique 4.3.3 Three-input adder 4.3.4 VCO-based quantizer 4.3.5 Integrator 4.3.6 DACs 4.3.7 Interface 4.3.8 Experimental results 4.4 Conclusions 5 Fully-VCO-based high-order DS ADCs 5.1 Introduction 5.2 Integrators 5.2.1 Traditional analog integrator 5.2.2 VCO-based integrator 5.2.3 Fully-VCO-based DS ADC structure 5.3 Design example: a fully-VCO-based 0-2 MASH VCO-based DS ADC 5.3.1 System architecture 5.3.2 Circuit implementation 5.3.3 Experimental results 5.4 Conclusions 6 Nantenna-based solar energy harvesting 6.1 Background and motivation 6.2 Traditional RF/microwave rectenna 6.3 Nano-rectenna and its efficiency 6.4 Prototype design: 160-GHz on-chip rectenna 6.4.1 Harmonic-rejecting on-chip antenna 6.4.2 CMOS rectifier 6.4.3 Measurements of the prototype chip 6.5 Conclusions 7 Conclusions 7.1 Summary and conclusions 7.2 Suggestions for future work Bibliographynrpages: 156status: publishe