Higher-Order Glitch Resistant Implementation of the PRESENT S-Box

© Springer International Publishing Switzerland 2015. Glitches, occurring from the unwanted switching of CMOS gates, have been shown to leak information even when side-channel countermeasures are applied to hardware cryptosystems. The polynomial masking scheme presented at CHES 2011 by Roche et al. is a method that offers provable security against side-channel analysis at any order even in the presence of glitches. The method is based on Shamir’s secret sharing and its computations rely on a secure multi-party computation protocol. At CHES 2013, Moradi et al. presented a first-order glitch resistant implementation of the AES S-box based on this method. Their work showed that the area and speed overheads resulting from the polynomial masking are high. In this paper, we present a first-order glitch resistant implementation of the present S-box which is designed for lightweight applications, indicating less area and randomness requirements. Moreover, we provide a second-order glitch resistant implementation of this S-box and observe the increase in implementation requirements.status: publishe