Convolution Based Steady State Compact Thermal Model for 3D Integrated Circuits: Methodology for Including the Thermal Impact of Die to Die Interconnections

Thermal analysis of integrated circuits in silicon chips is essential to avoid temperature driven reliability problems and failures: this is particularly important for 3D configurations with heat dissipated on several stacked dies. Finite element methods are traditionally used for this purpose. However, an efficient comparison of different chip designs requires faster methodologies, resulting in the development of various compact thermal models (CTMs). The method presented in this paper, to evaluate the temperature profiles on the active layers of two dies stacks, is based on the superposition principle applied through convolution and fast Fourier transform. This approach is valid if the heat path is independent of the heat dissipation horizontal position. However, boundary conditions and material non-homogeneity in the die-die interface layer, due to the integration of microstructures for die-die interconnections, cause this hypothesis to fail. The method of images is used to deal with the former issue while, to compensate for material non-homogeneity, a novel correction methodology is presented. It is based on fitting models created from finite element simulations of simplified structures with uniform power dissipation on one die and convective boundary condition on one side. Generalizations, allowing for convective boundary conditions on both sides and non-uniform power dissipations on both dies, follow. The presented CTM allows assessing the thermal impact of different parameters, power dissipation patterns and die-die interconnections placements in a user-friendly way. Comparisons of CTM results with 3D finite element models show a 30 times speed up and an inaccuracy smaller than 2%.status: publishe