Ultra Low Power High Speed SRAM Design

Modern mobile devices such as smart phones and laptops need large and fast memories for their multimedia-intensive applications. To obtain a long standalone time, the power used by these memories need to be minimized. This power consists of two parts: a constant leakage power and an active power which is only consumed when the memory is in use.The cost of the systems-on-a-chip used in these devices needs to be as limited as possible. For these reasons, and to obtain sufficient speed, highly scaled technologies are used. These systems-on-a-chip already consists for a large part out of memories. Every increase in memory area should be avoided. The same is true for adding power supplies. In addition, a few difficulties that impede the design of these memories arise when deep submicron technologies are used. The most important are leakage and variability.The goal of this work is to design high speed memories for use close to the CPU that use as little energy as possible. Different techniques to achieve this goal are discussed and some new methods are proposed.Leakage is reduced without compromising speed by increasing both threshold and supply voltage. To reduce unnecessary activity, word lines are divided and a distributed decoder is used. As the largest part of the active energy is used in the bit lines, different energy reduction techniques are applied. These include the use of divided bit lines with read buffers and local sense amplifiers, a dual swing data link method and a low swing write scheme.It is almost impossible to design low power memories without using at least one extra power supply. To avoid the cost of such a supply, an integrated charge pump topology is proposed. Dynamic stability is employed to guarantee robustness. A hybrid static/dynamic decoder is used to speed up the design.To prove the functionality of these techniques, two prototype memories were designed, fabricated and measured. State-of-the-art results were obtained.Voorwoord i Samenvatting iv Abstract v Table of contents vii List of abbreviations, signals and symbols xiii 1 Introduction 1 1.1 Memory hierarchy 2 1.2 Classic SRAM memory design 3 1.2.1 Memory cell 5 1.2.2 Memory matrix 5 1.2.3 Address decoder 7 1.2.4 Sense amplifiers 9 1.2.5 Bit line drivers 9 1.2.6 Control circuit 10 1.2.7 Results 11 1.3 Goal of this work 15 1.4 Strategy 16 1.5 Structure of this work 17 I Data storage 20 2 Memory cell 21 2.1 Cell specifications 22 2.1.1 Area 22 2.1.2 Writeability 22 2.1.3 Stability 22 2.1.4 Read speed 23 2.1.5 Standby power 23 2.1.6 Other specifications 23 2.2 Cell types 24 2.2.1 Dynamic cells 24 2.2.2 Static cells 24 2.2.3 Comparison of RAM cells 29 2.3 Operation and analysis of a 6T-cell 31 2.3.1 Data retention 32 2.3.2 Read operation 36 2.3.3 Write operation 39 2.4 6T-cell design parameters 40 2.4.1 Transistor sizing 40 2.4.2 Transistor threshold voltage 43 2.4.3 Supply voltage 43 2.4.4 Supply and threshold voltage 45 2.4.5 Bulk voltage 45 2.4.6 Word line voltage 49 2.4.7 Bit line voltage 49 2.4.8 Bit line capacitance 49 2.5 The future of the 6T-cell 53 2.6 Conclusion 53 II Data selection 56 3 Subdivided memory structure 57 3.1 Divided word lines 57 3.2 Divided bit lines 59 3.2.1 Full swing global and local bit lines 61 3.2.2 Low swing global and full swing local bit lines 63 3.2.3 Low swing global and local bit lines 65 3.3 Local blocks 65 3.3.1 Memory cell 66 3.3.2 Local GWL-LWL periphery 67 3.3.3 Local GBL-LBL periphery 67 3.3.4 Local control 69 3.4 Global sense amplifiers 70 3.5 Conclusion 72 4 Timing and decoding 73 4.1 Distributed decoder 73 4.1.1 Static implementation 75 4.1.2 Dynamic implementation 76 4.2 Timing 79 4.2.1 Requirements 79 4.2.2 Implementation 81 4.2.3 Long distance signaling 90 4.3 Merging timing and decoding 92 4.4 Conclusion 93 III Data transfer 96 5 Low energy data transfers 97 5.1 Basic voltage mode data transfers 99 5.1.1 Single-ended versus dual-ended data transfers 99 5.1.2 Full swing versus low swing data transfers 102 5.1.3 Unidirectional versus bidirectional data transfers 103 5.1.4 Energy-optimal low swing signaling 103 5.2 Advanced voltage mode data transfers 104 5.2.1 Dual-swing data transfer 104 5.2.2 Adiabatic charging and charge recycling 109 5.3 Generation of low voltage supplies 113 5.3.1 Charge pump topology and operation 114 5.3.2 Charge pump analysis 116 5.3.3 Charge pump optimization 117 5.4 Conclusion 121 6 Sense amplifiers 123 6.1 Sense amplifier specifications 124 6.1.1 Offset 124 6.1.2 Energy consumption 125 6.1.3 Input impedance 126 6.1.4 Area 126 6.1.5 Delay 126 6.2 Basic voltage mode sense amplifiers 126 6.2.1 Drain-input sense amplifier 126 6.2.2 Gate-input sense amplifiers 139 6.3 Advanced techniques for offset reduction 148 6.3.1 Sense amplifier redundancy 148 6.3.2 Charge pump sense amplifiers 151 6.4 Conclusion 153 IV Results 157 7 Test implementations 159 7.1 First prototype (65-nm low-standby-power technology) 159 7.1.1 General design 160 7.1.2 Operation 163 7.1.3 Local block implementation 165 7.1.4 Cell design 167 7.1.5 Dual-swing global bit lines 169 7.1.6 Dynamic decoder 172 7.1.7 Timing and control 174 7.1.8 Measurements 176 7.2 Second prototype (40-nm low-standby-power technology) 178 7.2.1 General design and operation 180 7.2.2 Signal ripple buffers 181 7.2.3 Peripheral circuits 183 7.2.4 Cell design and low swing writing scheme 183 7.2.5 Integrated charge pump 185 7.2.6 Simulation results and measurements 186 7.3 Third prototype (40-nm general-purpose technology) 190 7.3.1 Cell design and low swing writing scheme 191 7.3.2 Integrated charge pump 191 7.3.3 Simulation results and comparison 193 7.4 Conclusion 194 8 Conclusions and future work 195 8.1 Conclusions 195 8.2 Future work 197 A Variability analysis 201 A.1 Monte Carlo analysis 201 A.2 Sensitivity analysis 204 List of publications and biography 207 Bibliography 209nrpages: 244status: publishe