Algorithm Parallelization using Software Design Patterns, an Embedded Case Study Approach

Multicore embedded systems introduce new opportunities and challenges. Scaling of computational power is one of the main reasons for transition to a multicore environment. In most cases parallelization of existing algorithms is time consuming and error prone, dealing with low-level constructs. Migrating principles of object-oriented design patterns to parallel embedded software avoids this. We propose a top-down approach for refactoring existing sequential to parallel algorithms in an intuitive way, avoiding the usage of locking mechanisms. We illustrate the approach on the well known Fast Fourier Transformation algorithm. Parallel design patterns, such as Map Reduce, Divide-and-Conquer and Task Parallelism assist to derive a parallel approach for calculating the Fast Fourier Transform. By combining these design patterns, a robust and better performing application is obtained. © 2013 IEEE.status: publishe