Design of High-Bandwidth Low-Power Delta-Sigma Modulators (Ontwerp van delta-sigma modulatoren met hoge bandbreedte en laag vermogenverbruik)

This work focuses on the design of high-bandwidth low-power DSM ADCs, both at architecture level and circuit level. The first two designs are 40MHz-bandwidth 12-bit CT DSMs implemented in 90nm CMOS. The quantizations are done by the highly-digital phase-type VCO-based quantizer with 1st-order noise shaping. In the first design, the shaped switched-capacitor digital-to-analog converter (SC DAC) is proposed to relax the amplifier slew-rate requirement, and the look-up-table (LUT)-based digital calibration is presented to eliminate the distortion of the multi-bit SC DAC. With 960MHz sampling frequency and 69.6mW power, the DSM achieves 72.9dB SNDR. The second design is an improved design, where several techniques are applied to target lower power: a half-period delay instead of a full-period delay is assigned for the feedback to tolerate a larger phase shift in the loop filter; the current-sharing OTA is applied to reduce the power consumption in the analog integrators. The DSM reaches 69.7dB SNDR, with a power consumption of 45mW.This work also proposes a two-step open-loop VCO-based ADC architecture, which is a robust hardware-economic structure with an excellent figure-of-merit (FoM). The VCO-based quantizer nonlinearities are mitigated by distortion cancellation and input-swing reduction techniques. Because of the intrinsic DEM on the VCO-based quantizer output, the matching requirement of the DAC cells is greatly relaxed. Measurements of a 40nm CMOS demonstration show that the ADC achieves 59.5dB SNDR for a 40MHz signal bandwidth, with 1.6GHz sampling frequency and only 2.57mW power consumption, corresponding to an excellent FoM of 42fJ/Step.With state-of-the-art power efficiencies, the presented high-bandwidth ADCs are very suitable for application in next-generation communication standards, including VDSL2+, 802.11n and LTE.Acknowledgement i Abstract iii List of Abbreviations and Symbols v Contents ix List of Figures xiii List of Tables xix 1 Introduction 1 1.1 Background and motivation . . . . . . . . . . . . . . . . . . . . . 1 1.1.1 Communication evolution . . . . . . . . . . . . . . . . . . 1 1.1.2 CMOS technology . . . . . . . . . . . . . . . . . . . . . 4 1.1.3 Receiver architectures . . . . . . . . . . . . . . . . . . . 7 1.2 The research objective and major contributions of the thesis . . 9 1.3 The thesis organization . . . . . . . . . . . . . . . . . . . . . . 10 2 A/D Converters and Their Applications 13 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ix x CONTENTS 2.2 ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1 ADC speed . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.2 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.3 ADC FoM . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 ADC architectures . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.1 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.2 Two-Step ADC . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.3 Pipelined ADC . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.4 SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.5 Delta-Sigma ADC . . . . . . . . . . . . . . . . . . . . . 27 2.3.6 ADC architecture summmary and comparison . . . . . . 29 2.4 Application of ADC in communications . . . . . . . . . . . . 30 2.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3 Continuous-Time Delta-Sigma Modulators 39 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2 DSM basics: oversampling and noise-shaping . . . . . . . . . . 40 3.3 DSM structures . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3.1 Discete-time and continuous-time DSMs . . . . . . . . . 43 3.3.2 1st-order and higher-order DSMs . . . . . . . . . . . . . 47 3.3.3 Single-loop and MASH DSMs . . . . . . . . . . . . . . . 49 3.3.4 Single-bit and multi-bit DSMs . . . . . . . . . . . . . . . 51 3.3.5 Feedforward, feedback and hybrid DSMs . . . . . . . . . 55 3.3.6 Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.3.7 Feedin paths . . . . . . . . . . . . . . . . . . . . . . . . 56 3.4 CT DSM nonidealities and modeling . . . . . . . . . . . . . . . 57 3.4.1 Loop filter nonidealities and modeling . . . . . . . . . . 57 CONTENTS xi 3.4.2 DAC nonidealities and modelling . . . . . . . . . . . . . 63 3.4.3 Quantizer nonidealities and modeling . . . . . . . . . . 68 3.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4 VCO-Based ADCs 71 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.2 VCO-based quantizers . . . . . . . . . . . . . . . . . . . . . . . 72 4.2.1 Single-phase counting VCO-based quantizer . . . . . . . 72 4.2.2 Multi-phase counting VCO-based quantizer . . . . . . . 73 4.2.3 Frequency-type VCO-based quantizer . . . . . . . . . . 74 4.2.4 Phase-type VCO-based quantizer . . . . . . . . . . . . . 76 4.3 Closed-loop VCO-based DSMs . . . . . . . . . . . . . . . . . . 77 4.3.1 DSM with frequency-type VCO-based quantizer . . . . 78 4.3.2 DSM with phase-type VCO-based quantizer . . . . . . . 79 4.3.3 DSM with residual-cancelling VCO-based quantizer . . 80 4.4 Open-loop VCO-based ADCs . . . . . . . . . . . . . . . . . . . . 81 4.4.1 VCO-based ADC with background digital calibration . . 81 4.4.2 VCO-based ADC with counting and foreground digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.4.3 VCO-based ADC with PWM precoding . . . . . . . . . 84 4.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5 40MHz-BW 12-bit Low-Power CT DSMs in 90nm CMOS 87 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.2 A 40MHz-BW 12-bit CT DSM with digital calibration and shaped SC DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.2.1 Structure of the CT DSM . . . . . . . . . . . . . . . . . 89 5.2.2 Delta-Sigma modulator building blocks design . . . . . . 94 xii CONTENTS 5.2.3 Measurement setup and experimental results . . . . . . . 101 5.3 A 40MHz-BW 12-bit CT DSM with capacitive local feedback and current-sharing OTA . . . . . . . . . . . . . . . . . . . . . 104 5.3.1 System design of the 40MHz 12-bit CT DSM . . . . . . 106 5.3.2 Circuit design of the DSM building blocks . . . . . . . . 108 5.3.3 Measurement results and discussions . . . . . . . . . . . . 111 5.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6 A 40MHz-BW Two-step Open-loop VCO-based ADC with 42fJ/step FoM in 40nm CMOS 115 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.2 Architecture design of two-step open-loop VCO-based ADC . . 116 6.2.1 A two-step open-loop VCO-based ADC architecture . . 117 6.2.2 Nonidealities of the two-step open-loop VCO-based ADC 119 6.3 Circuit implementation of the two-step open-loop VCO-based ADC123 6.3.1 VCO-based quantizer design . . . . . . . . . . . . . . . 124 6.3.2 DAC and subtractor design . . . . . . . . . . . . . . . . 125 6.4 Experimental results and discussions . . . . . . . . . . . . . . . 129 6.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 7 Conclusions 137 7.1 Summary and conclusions . . . . . . . . . . . . . . . . . . . . . 137 7.2 Suggestions for future work . . . . . . . . . . . . . . . . . . . . 139 Bibliography 141 List of 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