DRAM Circuit Techniques for Low Energy, High Speed Memory Architectures (DRAM circuit technieken voor geheugen architecturen met een laag energieverbruik en een grote toegangssnelheid)

In deep sub-micron technologies with critical dimensions below 100nm, the impactof variability on circuit performance becomes unacceptably large. At the same time,novel applications such as high-end mobile devices require a significant reduction inenergy consumption per operation. Embedded memories are one of the most criticalbuilding blocks in these contemporary systems, and they are one of the most likelytechnical bottlenecks for further scaling.Typical low power mobile applications are implemented using a heterogeneousmulticore architecture at system level. A novel, dynamic ram based, memoryarchitecture is proposed for such systems, that could be used for scratchpad memoriesand datapads. This low power DRAM (LPDRAM) architecture can bring an energyconsumption improvement over existing implementations of level 2 and 3 memories.This work will focus on studying circuit level LPDRAM implementations for level 2scratchpads.Not every DRAM technology is suited to implement LPDRAM. This is due to thefocus put on improving the power consumption. This work studies implementationsfor two technologies: eDRAM and 3DDRAM. eDRAM technology offers higherdensity compared with SRAM at the cost of increased energy consumption andcomplexity. New optimized DRAM architectures are also being developed for use in3D interconnected systems, and should be suitable for mobile applications. This thesisproposes to use both technologies to implement LPDRAM, under the assumption thatsuch technologies becomes available.Different types of SRAM cells and DRAM matrices are studied, to show that themain limitation for using eDRAM is their latency, while stand alone DRAM matricesare mainly limited by their high dynamic energy per access. The electrical factorsresponsible for these differences (longer bitlines, larger memory matrices, etc...) areidentified, and the principles for a DRAM architecture alleviating these penalties isproposed. It is shown that in a typical embedded system working at a reasonably highspeed (around 1GHz in 90nm), using modified bitline architecture could bring a lowerstatic energy per bit as well as a higher density than embedded SRAM for L2 memories.Two prototypes are designed, demonstrating improved dynamic energy consumptionand density, when compared with state of the art SRAM matrices.List of Figures List of Tables 1 Introduction 1.1 General memory presentation 1.1.1 System level memory description 1.1.2 Memory figures of merit 1.1.3 Typical architecture description 1.1.4 Low power SRAM 1.2 DRAM introduction 1.2.1 Commodity DRAM 1.2.2 The DRAM cell 1.2.3 Alternative DRAM technologies 1.3 LPDRAM introduction 1.3.1 High level LPDRAM definition 1.3.2 LPDRAM implementation 1.3.3 Comparison with other memories 1.3.4 Summary 2 Low Power DRAM description 2.1 Topology of a LPDRAM architecture 2.1.1 Energy comparison between SRAM and DRAM 2.1.2 LPDRAM architecture impact on the dynamic energy 2.1.3 LPDRAM topology impact on latency and density figures 2.2 High level localblock description 2.2.1 Local bitline 2.2.2 Local wordline 2.2.3 Localblock 2.2.4 Local refresh 2.3 LPDRAM behavior estimation 2.3.1 Comparison against a typical low power SRAM architecture . 2.3.2 Refresh handling strategies 2.3.3 Technology impact on LPDRAM 2.3.4 LPDRAM space definition 2.4 Conclusion 3 LPDRAM implementation 3.1 Local reading implementation 3.1.1 Two DRAM reading mechanisms 3.1.2 Cross coupled RSA 3.1.3 Single transistor RSA 3.1.4 Charge transfer sense amplifier 3.2 Writing issues 3.2.1 Access transistor gate overdrive 3.2.2 Double phase writing 3.2.3 Write sense amplifier implementation 3.3 Local refresh implementation 3.3.1 1T1C DRAM refresh operation 3.3.2 Double cycle refresh operation 3.4 LPDRAM global peripherals 3.4.1 Global decoder architecture 3.4.2 Global refresh peripherals 4 LPDRAM prototypes 4.1 LPDRAM prototype using DRAM technologies 4.1.1 Fast DRAM circuit topology 4.1.2 Methodology 4.1.3 Results 4.2 2TDRAM implementation 4.2.1 Global Architecture 4.2.2 Refresh operation 4.2.3 Measurement results 5 Conclusions 5.1 Summary of the chapters 5.2 Conclusion 5.3 Future developments Bibliography List of publicationsnrpages: 160status: publishe