In this work, we report the selective area epitaxial growth of high quality InP in shallow trench isolation (STI) structures on Si (0 0 1) substrates 6° miscut toward (1 1 1) using a thin Ge buffer layer. We studied the impact of growth rates and steric hindrance effects on the nano-twin formation at the STI side walls. It was found that a too high growth rate induces more nano-twins in the layer and results in InP crystal distortion. The STI side wall tapering angle and the substrate miscut angle induced streric hindrance between the InP facets and the STI side walls also contribute to defect formation. In the [1 1 0] orientated trenches, when the STI side wall tapering angle is larger than 10°, crystal distortion was observed while the su...
The integration of III/V materials onto large scale Si substrates is of significant interest for mic...
Growth of InP with high crystalline quality on exact Si (001) substrates is reported. InP seed array...
To further boost the CMOS device performance, Ge has been successfully integrated on shallow trench ...
In this work, we report the selective area epitaxial growth of high quality InP in shallow trench is...
In this paper, we report a comprehensive investigation of InP selective growth in shallow trench iso...
Heterogeneous integration of III-V semiconductors on Si substrate has been attracting much attention...
We discuss the selective epitaxial growth of InP on patterned Si (001) substrates with Shallow Trenc...
In this work, we demonstrate the selective area growth of high quality InP layers in submicron trenc...
We report the selective area growth of InP layers in submicron trenches on Si (001) substrates by us...
This study relates to the heteroepitaxy of InP buffer on patterned Si substrates using the selective...
In this PhD work, the threading dislocation glide characteristics in Ge epitaxial layers have been s...
In the paper, we theoretically investigate a new size effect of trench width on inter-island distanc...
Junesand, Carl et al.Epitaxial lateral overgrowth of InP has been grown by hydride vapor phase epita...
Sub-22 nm high-performance digital circuits based on metal-oxide semiconductor (MOS) devices call fo...
The integration of III/V materials onto large scale Si substrates is of significant interest for mic...
The integration of III/V materials onto large scale Si substrates is of significant interest for mic...
Growth of InP with high crystalline quality on exact Si (001) substrates is reported. InP seed array...
To further boost the CMOS device performance, Ge has been successfully integrated on shallow trench ...
In this work, we report the selective area epitaxial growth of high quality InP in shallow trench is...
In this paper, we report a comprehensive investigation of InP selective growth in shallow trench iso...
Heterogeneous integration of III-V semiconductors on Si substrate has been attracting much attention...
We discuss the selective epitaxial growth of InP on patterned Si (001) substrates with Shallow Trenc...
In this work, we demonstrate the selective area growth of high quality InP layers in submicron trenc...
We report the selective area growth of InP layers in submicron trenches on Si (001) substrates by us...
This study relates to the heteroepitaxy of InP buffer on patterned Si substrates using the selective...
In this PhD work, the threading dislocation glide characteristics in Ge epitaxial layers have been s...
In the paper, we theoretically investigate a new size effect of trench width on inter-island distanc...
Junesand, Carl et al.Epitaxial lateral overgrowth of InP has been grown by hydride vapor phase epita...
Sub-22 nm high-performance digital circuits based on metal-oxide semiconductor (MOS) devices call fo...
The integration of III/V materials onto large scale Si substrates is of significant interest for mic...
The integration of III/V materials onto large scale Si substrates is of significant interest for mic...
Growth of InP with high crystalline quality on exact Si (001) substrates is reported. InP seed array...
To further boost the CMOS device performance, Ge has been successfully integrated on shallow trench ...