Investigation of the Electrical Properties of Ge/High-K Gate Stack (Onderzoek naar de elektrische eigenschappen van hoge-permittiviteitsdiëlectrica op Germanium)

High mobility channel materials have to be implemented in order to overcome future complementary-metal-oxide-semiconductor scaling bottleneck and allow further improvements in terms of transistor performance. Germanium is likely an attractive candidate as a channel material, owing to its high bulk hole and electron mobility. In addition, it has the advantage of process compatibility and easy integration with state-of-art Silicon CMOS technology. However, there are critical issues to be solved on device level before the integration of Germanium with Silicon CMOS becomes a viable solution. Germanium does not have a stable native insulator as its Silicon counterpart. As a result, getting a high interface quality between the substrate and the high-κ dielectric remains a challenge. The most difficult and long-standing problem is the Ge surface passivation of the defects that have been inevitably formed between the channel material and the high-κ dielectric deposited layer. In addition, the metal gate could have a large impact as well on the degradation of the device performance of the Ge/high-κ gate stack. Through physical and electrical analysis, several interface passivation approaches are further investigated, comparing different growth of the Ge oxide, different high-κ dielectrics deposition techniques, different metal gates and different device process flow. This Ph.D dissertation focuses on all these challenges, investigating Ge-related issues, providing understandings of the various mechanisms occurring in the Ge/high-κ gate stack. Solutions to move one step ahead in realizing Ge-based MOSFET devices for future high performance CMOS applications, while following the sub-1nm EOT scaling requirements, are proposed.Novel Materials for MOSFET devices: State-of-The-Art, Challenges and Limitations 1. 1. Motivation: Scaling Limit of Silicon-Based Technology 1. 2. Towards Germanium-Based Technology 1. 3. Novel CMOS Concepts – Channel Materials 1. 4. Germanium-Dielectric Interface 1. 5. Germanium-Metal Interface 1. 6. Devices and Basic Device Parameters 1.6.1. The MOS Capacitor 1.6.2. The Field Effect Transistor 1. 7. Goals of the Thesis 1. 8. Organization of the Thesis REFERENCES Properties of the Germanium Surface and Oxide Growth 2. 1. Introduction – Germanium Passivation Approach 2.2. Germanium Surface Preparation 2. 3. Investigation of the Germanium Oxide Growth 2. 4. Defects at the Ge/GeO2 Interface 2.4.1. Presence of a GeOX Transition Layer 2.4.2. Ge Dangling Bonds 2.4.3. Germanium Oxide Desorption Behaviour 2. 5. Solution for Enhanced Interface Quality 2.5.1. High Temperature Ge Oxidation 2.5.2. High Pressure Oxidation 2.5.3. Radical Oxidation 2.6. Processing Related Issues 2.6.1. Effect of Metal Gate Induced Stress 2.6.2. Effect of Metal Gate Wet Etch Treatment 2.6.3. Effect of Aggressive Lift-off 2.7. Summary and Conclusion REFERENCES Germanium/Dielectric Interface 3.1. Introduction 3.2. Investigation of the Ge/(GeO2/)high-ĸ Gate Stack by means of Molecular Beam Deposition 3.2.1. Basics of Molecular Beam Deposition 3.2.2. Process Flow Description of Capacitors Fabrication 3.2.3. Physical Characterization of the Interfacial Quality of the Ge/Al2O3 Stack 3.2.4. Electrical Characterization of the Interfacial Quality of the Ge/Al2O3 Stack 3.2.5. Physical Characterization of the Ge/GeO2/Al2O3 Stack 3.2.6. Electrical Characterization of the Ge/GeO2/Al2O3 Stack 3.2.7. Summary of the Ge/(GeO2/)Al2O3 Gate Stacks Investigation 3. 3. Investigation of the Ge(GeO2/)high-ĸ Gate Stack by means of Atomic Layer Deposition 3.3.1. Basics of Atomic Layer Deposition 3.3.2. Process Flow Description of Capacitors Fabrication 3.3.3. Physical Characterization of the Ge/GeO2/high-ĸ Stack 3.3.4. Electrical Characterization of the Ge/GeO2/high-ĸ Stack 3.3.5. Summary 3. 4. Summary and Conclusion REFERENCES FETs Performance for a Future CMOS GeO2-based Technology 4. 1. Introduction: Germanium, an enabling material for future high-performance CMOS technology 4. 2. Transistors Process Flow Description 4. 3. Investigation of Substrate Doping Influence 4.3.1. Doping Impact on Interface State Density 4.3.2. Doping Impact on Mobility 4. 4. Investigation of the GeO2 Interfacial Layer Quality 4.4.1. Impact of GeO2 Thickness 4.4.2. Impact of GeO2 Growth Temperature 4. 5. Defect Generation in Ge/GeO2/High-ĸ Gate Stacks 4.5.1. Interpretation of Trap Density 4.5.2. Defect generation in both Ge/Si/SiO2/HfO2 and Ge/GeO2/HfO2 stacks 4. 6. Defects in the High-ĸ Dielectric 4. 7. Impact of the High-ĸ Dielectric Deposition Technique 4.7.1. Efficiency of Radical oxidation/Molecular Beam Deposition Combination 4.7.2. Comparison between MBD and ALD Techniques 4. 8. Investigation of Hydrogen Passivation Properties of the Ge Surface 4.8.1. Introduction to Hydrogen Passivation Properties 4.8.2. Process Flow Description 4.8.3. Impact of H anneal on Dit at the Ge/GeO2 Interface 4. 9. Investigation of Post Metallization Annealing 4.9.1. Dit Behaviour 4.9.2. Annealing Condition Optimization 4. 10. Summary and Conclusion REFERENCES Sub-nm EOT Scaling Approach 5. 1. Introduction 5. 2. Use of CeO2 as alternative HiK for Ge passivation 5.2.1. Experimental details 5.2.3. Electrical Properties of CeO2-based stacks 5.2.4. CeO2/HfO2 Bi-layer Configuration 5.2.5. Learning on the CeO2-based stack 5. 3. Use of La2O3 as alternative HiK for Ge passivation 5.3.1. Structural and Physical Properties of the Ge/Ge(M)O2 Interfaces with M=La and Al 5.3.2. Electrical Properties of La-based Ge MOSFETs devices 5.3.3. La2O3/HfO2 Bi-layer Configuration 5.3.4. Learning on the La2O3-based stack 5. 4. Use of LaAlO3 as alternative HiK for Ge passivation 5.4.1. Processing Related Information 5.4.2. Physical Properties of the LaAlO3-based stack 5.4.3. Electrical Properties of LaAlO3-based Ge MOSFETs devices 5.4.4. Learning on the LaAlO3-based stack 5. 5. Use of HfO2 with High- Value 5.5.1. Physical Properties of Ge/HfO2 Interface 5.5.2. Electrical Properties of the Ge/HfO2 Interface 5. 6. Scaling Limit of GeO2-based Devices 5.6.1. Benchmarking: Gate Leakage 5.6.2. Benchmarking: Interface State Density 5.6.3. Benchmarking: Carrier Mobility 5.8.1. GeOXNY as Passivation Layer 5.7.2. Ge3N4 as Passivation Layer 5.7.3. H2S Molecular Beam Passivation of Ge 5. 8. Summary and Conclusion REFERENCES Conclusions 6.1. Summary 6.2. Main Conclusions of this Work 6. 3. Future Research Directionsnrpages: 220status: publishe