High-throughput programmable cryptocoprocessor

The key requirements of High-speed Internet Protocol security (IPsec) applications are high throughput and flexible security engines. A new high-throughput, programmable cryptoprocessor that runs the AES algorithm in different operation modes is designed to meet these requirements. The device achieves a maximum throughput of 3.43 Gbps at a 295-MHz clock frequency using 0.18-micron CMOS technology. The instruction set includes initialization, key setup, and AES encryption for different operation modes. Block pipeline instructions allow AES to run in ECB, CBC-MAC, counter, and CCM modes in 11 clock cycles per 128-bit block without loss in throughput compared to an AES without a mode of operation.status: publishe