The filling of microvias with diameters between 30 and 100 μm and aspect ratios up to 2.5 in silicon wafers, was investigated to determine the performance of copper electroplating. An electrolyte with a low leveler concentration was only suitable for filling microvias with aspect ratios below 1. An increase of the leveler concentration enabled the filling of microvias with higher aspect ratios. The fill-up evolution shows a bottom-up plating behavior. Electrochemical measurements show that for conditions prevailing at the bottom of the via, the electrodeposition rate is enhanced while for conditions prevailing at the top, it is inhibited. This difference originates from a concentration gradient of leveler inside the via and different convec...
abstract: This work demonstrates a capable reverse pulse deposition methodology to influence gap fil...
Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced ...
A micro-electroplating method to fabricate smallest interconnection bumps and highly dense routing l...
The filling of microvias with a diameter of 5 µm and a depth of 25 µm (aspect ratio of 5) by copper ...
This work explores the mechanism of microvia filling by copper electroplating using a printed circui...
Microvia interconnectors are a critical element of 3D packaging technology, as they provide the shor...
Microvia filling by copper electroplating was carried out using a plating bath containing a suppress...
We present two approaches to reduce the process time needed for filling vias of 5 µm diameter and 25...
International audienceIn order to anticipate the further demands of miniaturization and integration ...
International audienceIn order to anticipate the further demands of miniaturization and integration ...
International audienceIn order to anticipate the further demands of miniaturization and integration ...
The development of high density interconnects (HDI) for IC packaging substrate and printed circuit b...
High density interconnections (HDI) between multilayers and microvias are used in state-of-the-art p...
Nowadays, high performance of integrated circuits is owing its interconnections and packaging techno...
Electrochemical thermodynamics is the foundation of the microvia fill process, whose model represent...
abstract: This work demonstrates a capable reverse pulse deposition methodology to influence gap fil...
Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced ...
A micro-electroplating method to fabricate smallest interconnection bumps and highly dense routing l...
The filling of microvias with a diameter of 5 µm and a depth of 25 µm (aspect ratio of 5) by copper ...
This work explores the mechanism of microvia filling by copper electroplating using a printed circui...
Microvia interconnectors are a critical element of 3D packaging technology, as they provide the shor...
Microvia filling by copper electroplating was carried out using a plating bath containing a suppress...
We present two approaches to reduce the process time needed for filling vias of 5 µm diameter and 25...
International audienceIn order to anticipate the further demands of miniaturization and integration ...
International audienceIn order to anticipate the further demands of miniaturization and integration ...
International audienceIn order to anticipate the further demands of miniaturization and integration ...
The development of high density interconnects (HDI) for IC packaging substrate and printed circuit b...
High density interconnections (HDI) between multilayers and microvias are used in state-of-the-art p...
Nowadays, high performance of integrated circuits is owing its interconnections and packaging techno...
Electrochemical thermodynamics is the foundation of the microvia fill process, whose model represent...
abstract: This work demonstrates a capable reverse pulse deposition methodology to influence gap fil...
Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced ...
A micro-electroplating method to fabricate smallest interconnection bumps and highly dense routing l...