FPGA design of EKF block accelerator for 3D visual SLAM

International audienceThis paper deals with the evaluation of a dedicated architecture to be integrated into an embedded system typically mounted on a micro-aerial vehicle or on smart devices held by an operator. This system performs an Extended Kalman Filter (EKF) based visual odometry (VO) algorithm. An efficient hardware architecture conceived as a systolic array co-processor for EKF loop acceleration is presented. Due to severe limitations in terms of power consumption, real-time performance and physical characteristics of the system (i.e. compactness and weight), this algorithm is implemented entirely as a System On a programmable Chip (SoC) on the Zynq-7020 device. This heterogeneous (processor with reconfigurable hardware) platform consumes less power than a standard microprocessor and provides powerful parallel data processing capabilities: applying hardware/software (hw/sw) co-design allows real-time throughput with a very low power-per-feature rate