\u3cp\u3eTracking the gradual effect of silicon aging requires fine-grain slack monitoring. Conventional slack monitoring techniques intend to measure worst-case static slack, i.e. the slack of longest timing path. In sharp contrast to the conventional techniques, we propose a novel technique that is based on dynamic excitation of in-situ delay monitors, i.e. dynamic excitation of the timing paths that are monitored. As the delays degrade, the path delays increase and the monitors are excited more frequently. With the proposed technique, a fine-grained signature of the delay degradation is extracted from the excitation rate of monitors.\u3c/p\u3
Precise measurement of digital circuit degradation is a key aspect of aging tolerant digital circuit...
With the scaling of CMOS technology, critical paths in digital circuits have become largely sensitiv...
In the post-silicon stage, timing information can be extracted from two sources: (1) on-chip monitor...
Tracking the gradual effect of silicon aging requires fine-grain slack monitoring. Conventional slac...
\u3cp\u3eIn-situ delay monitoring is an advanced technique to monitor the robustness of digital circ...
Abstract—In situ monitoring is an accurate way to monitor circuit delay or timing slack, but usually...
Abstract—In situ monitoring is an accurate way to monitor circuit delay or timing slack, but usually...
Aggressive technology shrinking has increased the sensitivity of integrated circuits in terms of dev...
International audienceAging induced degradation mechanisms occurring in digital circuits are of a gr...
International audiencePVT information is mandatory to control specific knobs to compen-sate the vari...
International audiencePVT monitors are mandatory to use tunable knobs designed to compensate the var...
Conference of 20th IEEE International On-Line Testing Symposium, IOLTS 2014 ; Conference Date: 7 Jul...
Aggressive technology scaling has accelerated the ageing of CMOS devices. Ageing refers to a slow pr...
Interconnection reliability threats dependability of highly critical electronic systems. One of most...
Aggressive technology scaling has accelerated the susceptibility of CMOS devices to aging effects. C...
Precise measurement of digital circuit degradation is a key aspect of aging tolerant digital circuit...
With the scaling of CMOS technology, critical paths in digital circuits have become largely sensitiv...
In the post-silicon stage, timing information can be extracted from two sources: (1) on-chip monitor...
Tracking the gradual effect of silicon aging requires fine-grain slack monitoring. Conventional slac...
\u3cp\u3eIn-situ delay monitoring is an advanced technique to monitor the robustness of digital circ...
Abstract—In situ monitoring is an accurate way to monitor circuit delay or timing slack, but usually...
Abstract—In situ monitoring is an accurate way to monitor circuit delay or timing slack, but usually...
Aggressive technology shrinking has increased the sensitivity of integrated circuits in terms of dev...
International audienceAging induced degradation mechanisms occurring in digital circuits are of a gr...
International audiencePVT information is mandatory to control specific knobs to compen-sate the vari...
International audiencePVT monitors are mandatory to use tunable knobs designed to compensate the var...
Conference of 20th IEEE International On-Line Testing Symposium, IOLTS 2014 ; Conference Date: 7 Jul...
Aggressive technology scaling has accelerated the ageing of CMOS devices. Ageing refers to a slow pr...
Interconnection reliability threats dependability of highly critical electronic systems. One of most...
Aggressive technology scaling has accelerated the susceptibility of CMOS devices to aging effects. C...
Precise measurement of digital circuit degradation is a key aspect of aging tolerant digital circuit...
With the scaling of CMOS technology, critical paths in digital circuits have become largely sensitiv...
In the post-silicon stage, timing information can be extracted from two sources: (1) on-chip monitor...