Practical considerations for the design of cascade multi-bit high-frequency /spl Sigma//spl Delta/ modulators

Recommendations are given for efficient design of high-frequency /spl Sigma//spl Delta/ modulators using multi-stage (cascade) multi-bit quantization architectures. These cover from pure architectural aspects to cell design with special emphasis on the impact of circuit imperfections. Conclusions are validated by measurements on a 13-bit 2.2 MS/s prototype fabricated in a 0.7 /spl mu/m CMOS technology.Comisión Interministerial de Ciencia y Tecnología TIC 97-058