Serial bus adapter design for FPGA

In recent years, FPGAs (Field Programmable Gate Arrays) have become a popular platform for testing and implementing hardware designs by increasing their capacity and cost efficiency in the competition with Application Specific Integrated Circuits (ASICs). Processors can be used for any problem but they have not been optimized for specific problems. The design of ASIC is an extremely complex task, very time consuming and expensive; they are used for mass products. FPGA is an intermediate solution between general purpose processors and ASICs. Altera Cyclone V 28nm is a System On Chip (SoC), which integrates a Hard Processor Core (HPS), peripherals, and memory controller with the FPGA fabric. However, HPS consist of only one-directional serial data (SDA) buses and serial clock (SCL) buses and provides support for a communication link only between integrated circuits on a board. It is necessary to build an I2C serial bus adapter in order to communicate between HPS and other devices outside the board. I2C serial bus adapter is implemented and tested in this thesis. It adapts the communication from one-directional serial data line of hard processor system to bi-directional data line. In order to test the I2C adapter in both writing data operation and reading data operation, Signal Generator blocks to generate testing signals are implemented and I2C Slave block from OpenCores to detect and display data to LEDs is used. All the blocks are implemented in VHSIC Hardware Description Language (VHDL). The verifications for I2C Adapter, Signal Generator and I2C Slave are inspected by waveforms on Modelsim SE 10.2c simulator. The block implementations are compiled and programmed by Quartus II 13.1 to DE1-SoC FPGA development board. DE1-SoC board buttons and LEDs are used to test the I2C adapter operation by a user. The results show that the adapter works as specified