Optimal clock period FPGA technology mapping for sequential circuits

Abstract � In this paper � we study the technology mapping problem for sequential circuits for LUT� based FPGAs. Existing approaches map the combi� national logic between �ip��ops �FFs � while assum� ing the positions of the FFs are �xed. We study in this paper a new approach to the problem � in which retiming is integrated into the technology mapping process. We present a polynomial time technology mapping algorithm that can produce a mapping so� lution with the minimum clock period while assuming FFs can be arbitrarily repositioned by retiming. The algorithm has been implemented. Experimental re� sults on benchmark circuits clearly demonstrate the advantage of our approach. For many benchmark circuits � our algorithm produced mapping solutions with clock periods not attainable by a mapping al� gorithm based on existing approaches � even when it employs an optimal delay mapping algorithm for combinational circuits.