FROM FAULT TREE ANALYSIS TO MODEL CHECKING OF LOGIC CONTROLLERS

Abstract: This paper proposes a method enabling to state formal properties of a logic controller, a prerequisite for formal verification using model-checking, from a fault-tree analysis taking into account both the controlled process and the controller. Invariants, untimed and timed properties are considered and illustrated thanks to an example. The aim of this method is to ease formal properties design and to bridge the gap between fault forecasting and fault removal for automated systems. Copyright © 2005 IFA