Computer Engineering

Automation of wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism in a chip CE-MS-2007-14 Ardy van den Berg To find manufacturing defects, chip structures need to be tested. A test consists of test patterns which are generated at design time and stored in Automatic Test Equipment (ATE). A pattern contains stimuli bits and expected responses. For each pattern, the stimuli are applied to the chip. The corresponding responses are compared with the expected responses to detect defects in the chip. Most modern chips are composed of different modules which together form a System-on-Chip (SoC). Each module can be tested individually using isolation hardware called a wrapper. Stimuli and responses travel through the chip to and from the embedded module using a Test Access Mechanism (TAM). The conventional method uses wires dedicated for test purposes as TAM. In this work we propose to reuse an existing functional interconnect, such as a bus, a Network-on-Chip (NoC) or other functional interconnect as a TAM. Existing wrapper theories and algorithms covering the wrapper architecture, test length and idle bits have been extended and improved. Furthermore, a program has been built to automatically generate wrappers optimized for minimal test length, that reuse the existing functional interconnect as TAM. The program analyses a given module and the test infrastructure and builds a wrapper in VHDL code. The functionality of the generated wrapper has been verified via simulation. The program can be used by designers to improve the scan chains in a module, to decrease the test length. 200