Accelerating Relaxation Algorithms for Circuit Simulation Using Waveform Newton, Iterative Step Size Refinement, and Parallel Techniques Abstract

A high speed MOS digital circuit simulation program PNAP-1 (Parallel Network Analysis Program) implemented on a special-purpose parallel computer system LINKS-1 is described. In LINKS-1, 64 node computers are linked radially to a root computer through a very fast memory swapping unit. The task of the root computer is to control node computer and to store waveforms. Each node computer solves assigned subcircuit with standard circuit simulation techniques. PNAP-1 adopts a block-type waveform relaxation technique as a vehicle of the parallel computation of required waveforms. The slow convergence or more serious non-convergence problem inherent to relaxation-based methods is alleviated by analyzing tightly coupled portions in direct manner in conjunction with exploiting the overall quasi-unidirectional property of MOS digital circuits. A number of experimental results show that PNAP-1 can achieve a substantial speed improvement in the cost-effective analysis of VLSI circuits